the difference of the input and output constraints between altera and xilinx ?

[zlan01]

previously, I used xilinx fpga,now I am using altera fpga,the xilinx implement the input and output delay via the element in IOB block;

and how altera implement the input and output delay?

or is it via using different element in fpga to construct the function block to change the distance between the used element in fpga and the input and output ports to change the delay time?