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Valued Contributor III

the "R" ,"F" of the chip planner ?  


can you tell me that  

1 : what is the mean of the "r" ,'f', such as the R : 4.449ns, f:3.984ns,  

2 :is the red Vertical line and the red level line global clk ?? 

3 : If I want to see the delay from cell to output pin ,how i do ? 

thank you
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Valued Contributor III

Re: the "R" ,"F" of the chip planner ?

Rise delay and Fall delay. 

The red vertical lines I believe are because you clicked on Show Physical Routing, so it's trying to do that.  

I do not use Chip Planner to explore timing directly. I pretty much always use TimeQuest to look at the timing, and then will select path/s from a report_timing command and right-click Locate to Chip Planner. The TimeQuest report breaks timing numbers out in a much more readable way, not only with better details but with the whole "big picture" of how the path is analyzed. The Chip Planner then allows me to see the X/Y hops and visualize what's going on.
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