Hi,I observed the following behaviour using Quartus 17.0. When i start to add my own custom IP into the qsys, then the time_limited sof file is generated and the behaviour of my eclipse program is not the same anymore. 1. Where can I find the evaluation timeout? 2. Why is there a different sof(time limited) file generated once I add my own IP? 3. There seems to be a functional difference between a time_limited_sof and the .sof. I do the following. I receive over the UART IP core some data values and loop them back in the NIOS-II using a small c-program. This is working fine when I do not use my own IP core in the design, as soon as I include my own IP core the time_limited_sof is generated, but from this point of time the loopback on the UART is not working anymore. In both cases I use the same c-program, sure I have different system.h files due to the fact that one my IP core is in the design, once it not included in the design. My c-program does not access my IP core instance, so the software is independent from the usage of my IP core. Any idea where I could look for understanding this behaviour ? Thanks in advance!
Are you using Lite or Standard edition of Quartus? If Standard, do you have a license? Are you using the economy (free) or fast (licensed) version of Nios II?
--- Quote Start --- Which version of the Nios II core are you using and what's your target device? --- Quote End --- I am using the Altera Max 10 Fpga and the Nios2 core i am using is NIOS II/e
Can you go to the assembler report and check the "Encrypted Cores Summary"?If you don't know how to get it, go to the "Tasks" view on the left, and in the hierarchical list open "Compile Design", then "Assembler (Generate programming files)" and double-click on "View Report". Then in the report, choose "Encrypted Cores Summary". It should show you a list of all the cores that you used that require a license. It should tell you exactly which core you used that made your sof file time limited.