Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Valued Contributor III
1,838 Views

timeQuest timing analayzer

Hi All 

I successfully finished a full processing analysis for my design circuit, the clock in timeQuest timing analayzer indicate that the (max. freq.=443.07 MHz) where the Restricted FMax. is 250(note; i used the cycloneiii famlly. As listed in the Appendix below) .How can I overcome this problem.
0 Kudos
8 Replies
Highlighted
Valued Contributor III
2 Views

 

--- Quote Start ---  

Hi All 

I successfully finished a full processing analysis for my design circuit, the clock in timeQuest timing analayzer indicate that the (max. freq.=443.07 MHz) where the Restricted FMax. is 250(note; i used the cycloneiii famlly. As listed in the Appendix below) .How can I overcome this problem. 

--- Quote End ---  

 

You can't. It is basically saying that they really don't guarantee that anything will work correctly above 250 MHz.
0 Kudos
Highlighted
Valued Contributor III
2 Views

i think restricted fmax can indicate timing failures in macro timing models. for example, RAM or DSP blocks may have a large black box type of timing model rather than modelling individual paths in the block 

 

as KJ indicated, you can't work around this without rearchitecting (which may mean changing RAM block modes, etc)
0 Kudos
Highlighted
Valued Contributor III
2 Views

 

--- Quote Start ---  

the Restricted FMax. is 250 

--- Quote End ---  

 

I'm fairly sure that you use multipliers in your project which are restricted to 250 MHz (in 18x18 mode) in devices with speedgrade 7. See for yourself: 

http://www.altera.com/literature/hb/cyc3/cyc3_ciii52001.pdf 

(section "Embedded multipliers").
0 Kudos
Highlighted
Valued Contributor III
2 Views

Thanks Mr. AndrewS6 for this information . But how can I overcome these forms ( change this Fmax). if i have the cyclone iii kit only.

0 Kudos
Highlighted
Valued Contributor III
2 Views

I didn't follow exactly what you are trying to achieve. But if you want your design to operate at frequencies higher than 250. Then you have to re-architect it so that the RAM/DSP blocks can be operated at less than 250. Generally, this would mean you have to make that portion of the design operate in parallel with more instances of the same pipeline. But this is not always so, which is what make this problem interesting.

0 Kudos
Highlighted
Valued Contributor III
2 Views

Thanks for your advice . But i need my design to be faster(means higher Fmax) .

0 Kudos
Highlighted
Valued Contributor III
2 Views

use an Arria or Stratix

0 Kudos
Highlighted
Valued Contributor III
2 Views

thak yuo very much mr. thepancake ,i tryaing to do this .

0 Kudos