timing simulation problem!!!

[Altera_Forum]

hi all ! 

 I've designed a simple circuit and made a functional simulation. It seemt working how I want. But in timing simulation it didnt worked truly. So what do you think the problem is? :confused:    Thanks for your replays..

[Altera_Forum]

Hi, 

 For a good starting practice in problem solving, I suggest that you first identify the problem.  First convince the forum that the functional simulation does work then convince the forum that it is indeed the timing to blame.  If you blame the timing simulation make sure you are reading the waveforms corrctly and that your clock speed is not exceeding your Fmax.   Good luck

[Altera_Forum]

You'll want to go through the online training for timequest, but here is a good starter app note. Take your time. Timequest is a big cookie to crumble.  

 http://www.altera.com/literature/hb/qts/ug_tq_tutorial.pdf  Do a couple of simple examples and that may be enough for you if you are starting out and your design is relatively slow (say under 20 MHz).   Here's another good starter guide. http://www.alteraforums.com/forum/showthread.php?p=2574  I doubt you will make it very far until you do some basic reviews like these.  Your design may very well work just fine, especially if it's fairly slow and isn't clock rate dependent, but to properly constrain it you have to learn to use Timequest and write sdc files.

[Altera_Forum]

--- Quote Start ---   Do a couple of simple examples and that may be enough for you if you are starting out and your design is relatively slow (say under 20 MHz).    Here's another good starter guide. http://www.alteraforums.com/forum/showthread.php?p=2574   I doubt you will make it very far until you do some basic reviews like these.   Your design may very well work just fine, especially if it's fairly slow and isn't clock rate dependent, but to properly constrain it you have to learn to use Timequest and write sdc files.  --- Quote End ---     Thanks for your replay.   Yes you're right. I've decreased the speed of input signals and then the design worked properly..    Thanks for your advice :rolleyes: ;)