top level block symbol map question

[Altera_Forum]

Hi, 

 I have a project written in Verilog. The top level (CPU) connects several lower level components with lots of signals to connect. is there any way in quartus to make a printable diagram that shows all components with in/outputs and the signal wires connecting them? Thank you!

[Altera_Forum]

Have a look at the RTL view from netlist viewers in tools menu.

[Altera_Forum]

Hi, 

 You can use RTL viewer to see all IO the and also you can print.  For internal signal, i have used model-sim during debugs dataflow option.  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation) https://www.alteraforum.com/forum/attachment.php?attachmentid=14672 https://www.alteraforum.com/forum/attachment.php?attachmentid=14673

[Altera_Forum]

Thank you all. Yes, I'm trying to use RTL viewer. but it's not great. What I really want is a bow for each component with internals labeled inside and the wires connecting each component labeled. RTL view kind of does this, but in order to display all in/out connections I have to expand each component. When I expand it blows up the gate-level building blocks. I really just want a quick printable reference of how all of the 40-50 signals connect to all the in/outs of each component in the project. 

 Thank you! Jon

[Altera_Forum]

Anand, your second image may be what I'm after but the resolution is too small to tell for sure. Do you know the general options you used to get there?

[Altera_Forum]

Hi, 

 If you are having multiple module in you design integrated in top module you can see the integration of all modules.  RTL viewer first show the top module with IO/ports like first image->click on the + symbol on the top left of the module block shown in the RTL viewer  to view the sub modules like second image.   Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)

[Altera_Forum]

thank you so much!!! 

  --- Quote Start ---  Hi,  If you are having multiple module in you design integrated in top module you can see the integration of all modules.  RTL viewer first show the top module with IO/ports like first image->click on the + symbol on the top left of the module block shown in the RTL viewer  to view the sub modules like second image.   Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)  --- Quote End ---