unable to reuse design partition in quartus 19.3 version.

[DChak3]

Hi It seems there is an issue to reuse the design partition in quartus 19.3 version.

As while using the .qdb file it takes the file. But in netlist viewer I am unable to see the design connected. I have generated and reused .qdb file many times in 18.2 version but never faced this issue. I am not sure is any thing more need to be done in the latest version.

Also while reusing the design I am not able to see "set as design partition" in the window. which was available in 18 version.

[KhaiChein_Y_Intel]

Hi,

Could you share the error message?

Thanks.

[DChak3]

hi

Its not the error. Instead the .qdb file is not getting connected if seen in the rtl viewer.

Here are the steps which I followed.

1. Create a project add all the rtl files. Run analysis and synthesis once.
2. In the hieracrchy tab the module which I need to create a partition, right click it go to design partition, select default.
3. Run synthesis again, once done. Go to projects > export design partion> export the synthesised snapshot of the module.

To resue:

1. create a project with top file and the resuse module stub file.
2. run synthesis once.
3. follow the step no. 2 above to set the module to default.
4. int he desin partion window add the .qdb file and run the synthesis again

these steps I followed for Quartus 18. which was perfectly reusign the design. But here seems some issue with the .qdb file.

Added scrrenshots.

I have double checked there is no issue with the stub file, I am using all signals are same. I also tried running the whole flow till fitter but the results are same. As you can see once I add the qdb file. It is not getting connected to the design.

[DChak3]

Here are more screen shots

1. this the rtl view before qdb. only the top file and the partitioned stub file.

2. this the rtl view after adding the qdb

so u can see the partitioned files are not getting connected. The same procedure I gave done with quartus 18. There was no any issue. But here I can see that. Is there any thing I am missing.

[KhaiChein_Y_Intel]

Hi,

Can you provide the design and steps to reproduce the error?

Thanks.

[DChak3]

Hi

Thanks for response. It seems the problem was from my side in top level file. It resolves now.

[KhaiChein_Y_Intel]

Hi,

It is glad that you found the root cause.

Thanks