uniphy OCT_RUP and OCT_RDN

[Altera_Forum]

How to assign these two pins on top? 

can these two pin be assigned to the pins used by termination_blk0~_rdn_pad termination_blk0~_rup_pad for ALTMEMPHY? thanks

[Altera_Forum]

Hi, 

I'm working on a DDR3 design with UNIPhy on Stratix iv. These pins you must assign to any bank with the same I/O voltage as the memory interface signals (see External Memory Interface Handbook Volume 5, Section II. UniPHY Design Tutorials, page 2-2). Some deticated pins ar not usable for OCT, see pin connection guide for the device you are using. (i.e. the CLK[1,3,8,10]p pins in case of stratix iv ). The attached images show the toplevel and pin connections in an example design based on the Stratix iv GX Devkit wich I'am using actually.  Jens

[Altera_Forum]

yes. these two pins just like termination_blk0~_rup_pad in altmemphy 

the difference is calibration logic is generated in megawizard for uniphy.