I have some questions I have a matlab code which i want to convert it to VHDL code.
The idea in the matlab is using for loop where i compute some matrices by using some vectors I have already constructed.
for example if I have syst_bit=[1 2 3 4 5 .......], parity1=[1 2 3 4 5......] and parity2=[1 2 3 4 5......] I will use for loop as follows
for i=1:256
gamma(i)=syst_bit(i)+parity1(i);-- this is simplification equation
end;
for i=1:256
alpha(i)=syst_bit(i)*gamma(i);-- this is simplification equation
end;
for i=1:256
beta(i)=syst_bit(i)*gamma(i);-- this is simplification equation
end;
This should be done for constant number of times on VHDL while receiving the new input to construct new frames (both are done at the same time)
so my idea is creating the needed adders, multipliers, comparators ......
and using for loop in VHDL and on each loop I should put the input on the input wires of this blocks for example
for i in 0 to 255
wire1<=syst_bit(i);
wire2<=parity1(i);
gamma(i)<=wire3;
end loop;
is this right or not?
