use verilog module in vhdl and the test bench

Altera_Forum · ‎02-01-2016

I am trying to instantiating a verilog module in a vhdl design. There is no error shown after compile it but i can't get the corresponding result in the modelsim.

Does anyone can help me to check the code please?

The verilog module is:

module i2c (             CLOCK,
             I2C_SCLK,        //I2C CLOCK
             I2C_SDAT,        //I2C DATA
             I2C_DATA,        //DATA:
             GO,              //GO transfor
             ENDS,            //ENDS transfor 
             W_R,             //W_R
             ACK,             //ACK
             RESET,
             //TEST
             SD_COUNTER,
             SDO
               );

and I declare the component in vhdl is :

component i2c     port(
         CLOCK : in std_logic;
         I2C_SCLK : out std_logic;
         I2C_SDAT : inout std_logic;
         I2C_DATA : in std_logic_vector(23 downto 0);
         GO    : in std_logic;
         ENDS : out std_logic;
         W_R : in std_logic;
         ACK : out std_logic;
         RESET : in std_logic;
         -- TEST
         SD_COUNTER : out std_logic_vector (5 downto 0);
         SDO : out std_logic
    );
    end component;

When I use the testbench to simulate the code, The counter doesn't work. I don't know whats happening...

http://i.imgur.com/wuzwbxf.png

Does anyone can help me?

Altera_Forum · ‎02-01-2016

The GO control bit is active low.

Altera_Forum · ‎02-01-2016

plus - the reset is also active low.

Altera_Forum · ‎02-02-2016

Thank you for your reply! I didn't realize the reset is active low, thank you so much!

However, I have another question about the I2C.v, I know I shouldn't ask it in here...

Why I2C_SDAT is in high impedance if SDO is '1'? Is that means I2C_SDAT can't transmit the data?

wire I2C_SDAT = SDO?1'bz:0 ;

I search it on google already and there is the same question but I still don't understand...

http://www.alteraforum.com/forum/showthread.php?t=20018 (http://www.alteraforum.com/forum/showthread.php?t=20018)

Altera_Forum · ‎02-02-2016

Thank you so much, the problem is solve and the counter is working. Thank you!

Altera_Forum · ‎02-02-2016

--- Quote Start ---

Thank you for your reply! I didn't realize the reset is active low, thank you so much!

However, I have another question about the I2C.v, I know I shouldn't ask it in here...

Why I2C_SDAT is in high impedance if SDO is '1'? Is that means I2C_SDAT can't transmit the data?

wire I2C_SDAT = SDO?1'bz:0 ;

I search it on google already and there is the same question but I still don't understand...

http://www.alteraforum.com/forum/showthread.php?t=20018

--- Quote End ---

Because the designer chose to do everything active low without naming his signals appropriately or documenting the fact in the comments. Thats the only reason I can think of