hi,
i'm using stratix IV FPGA to implement my design. after doing the synthesis and analysis task with quartus, i generated the post synthesis file written in verilog to see how my design is synthesized. actually, in this file, there are modules which are instanciated called "stratixiv_ram_block". i find this component in the altera_mf library.but actually it is not a leaf component, i mean that, this stratixiv_ram_block is a function which will use other basic ram blocks like M9K, M144K.....so my question is, how to synthesize my design and oblige the synthesizer to use leaf block rams instead of megafunctions like stratixiv_ram_block???
and where to find those components in the altera library??(i mean M9K.v, M512.v....??)
thank you in advance
