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Greetings everyone, I want to divide a 50 MHz clock frequency by (2,3,4,5,6,7,8). I am using a Block Diagram Schematics. Can I do this by using a (Counter)?? I have tried using the (modulus) but I don't get any output in the Simulation. What can I do please?? I have been using VHDL for a long time, but now I want to accomplish the task using Block Diagram/Schematics because I don't want to go back to the coding.
Your help means a lot to me, Thanks!Link Copied
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Why dont you want to go back to coding? Block diagrams have many disadvantages over code:
1. You cannot simulate a block diagram (it has to be converted to HDL first) 2. Block diagrams are not portable between vendors 3. Block diagrams dont work very well with version control. Using a counter is possible to do anything - but I suggest not using the mod function - it implements a divider which may complete in a single clock and be very slow. And you should not generate a clock with logic anyway. It is much better practice to create a clock enable so that all logic uses the system clock, only enabled when required (every other clock, every third clock etc).- Mark as New
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Thank you very much indeed. But how do I use the clock enable input???? I mean there is the output from the pll that is connected directly to the clock of the counter. What do I have to connect to clk_enable input???
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you would have a counter free running, and then use the counter to generate a clock enable:
for example - to divide a clock by 16 - eg in VHDL:
signal counter : unsigned(3 downto 0);
signal clk_en : std_logic;
process(clk)
begin
if rising_edge(clk) then
counter <= counter + 1;
if counter = 0 then
clk_en <= '1';
else
clk_en <= '0'
end if;
if clk_en = '1' then
-- logic here is only switched on every 16 clocks
end if;
end if
end process;
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Thank you very much, that is really helpful.
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