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Altera_Forum
Honored Contributor I
1,095 Views

variable initialization help

Hi all, 

 

For a process, the variable only take the initial value at the first time the process is running, then it will take the last value of that variable. I am wondering how can I initial the variable every time the process is executed? 

 

For example, if I want to do something like following 

 

ENTITY example IS PORT ( ...... InitVal : IN INTEGER; -- initial value ...... ); ARCHITECTURE rt OF example IS ...... PROCESS (...) VARIABLE v1 : INTEGER := InitVal; BEGIN if (v1 < 100) then v1 := v1 + 1; end if; ...... END PROCESS; END ENTITY;  

 

InitVal is the integer input from upper level module, I want the variable v1 has the value of InitVal every time the process is executed. What can I do in this case? 

 

Many thanks for the help.
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9 Replies
Altera_Forum
Honored Contributor I
79 Views

Processes dont get "executed" they are in infinite loop starting at time 0.  

Do you mean you want to set v1 to init val every time the process is re-evaluated? 

 

why not just set v1 to initval before the if statement?
Altera_Forum
Honored Contributor I
79 Views

Hi,  

 

I mean that I want to set v1 to InitVal every time the process is re-evaluated. 

 

If I set v1 before the if statement, what about the clocked process something like following: 

ENTITY example IS PORT ( clk : IN STD_LOGIC; initval : IN INTEGER; ... ); END ENTITY; ARCHITECTURE rt OF example IS ... ex: PROCESS (clk) VARIABLE v1: INTEGER; BEGIN IF (rising_edge(clk)) THEN v1 := initval; ---------------------------- if I initialize here IF (v1 < 100) THEN v1 := v1 + 1; END IF; END IF; END PROCESS; END ARCHITECTURE;  

 

Will the value of v1 be initialized to initval at every clock edge in this case? 

 

Thank you for the help.
Altera_Forum
Honored Contributor I
79 Views

 

--- Quote Start ---  

 

Will the value of v1 be initialized to initval at every clock edge in this case? 

 

--- Quote End ---  

 

 

Yes. 

Is there any reason you are using variables rather than signals?
Altera_Forum
Honored Contributor I
79 Views

I have no preference between signals and variables.  

 

I am wondering is there any difference between signals and variables in terms of Fmax in this case? 

 

Thanks.
Altera_Forum
Honored Contributor I
79 Views

The use of signals and variables will have no difference in the end result IF you coded them the same. 

I advise against variables because they can be affected by code order, and could produce logic you didnt intend. There is NOTHING you can do with variables you cannot do with signals, and signals are more likely to give the intended result, and hence why it's recommended for beginners to NEVER use varibales. Remember, this is NOT software.
Altera_Forum
Honored Contributor I
79 Views

Many thanks for your help! 

 

For the example I have above, where to initialize the signal v1? 

 

ENTITY example IS PORT ( clk : IN STD_LOGIC; initval : IN INTEGER; ... ); END ENTITY; ARCHITECTURE rt OF example IS SIGNAL v1 : INTEGER := initval; ------------------------- If I initialized here ... ex: PROCESS (clk) BEGIN IF (rising_edge(clk)) THEN IF (v1 < 100) THEN v1 <= v1 + 1; END IF; END IF; END PROCESS; END ARCHITECTURE;  

 

If I initialized there, suppose I input 1 on port initval at clock edge 1, and the v1 will keep increase until 100 at every clock edge. However, if I input a new value at some other clock edge, how does this will effect the process?
Altera_Forum
Honored Contributor I
79 Views

You havent really said what you wanted to do. Even in the previous example, you code simply adds 1 to initval, so v1 is always initval + 1. It will not increment. You need some enable signal to mark when you actually want to assign the initval.

Altera_Forum
Honored Contributor I
79 Views

What I am doing is to implement the merge sort between two true-dual-port RAMs. RAM1 stored the initial data, and RAM2 is empty at the beginning. 

 

The Merge sort operation need to take two RAM1 data and store to the RAM2 in order after comparison. 

 

What I want to do is a component which did take the number and compare operations. And use a state-machine to pass the proper parameters such as the starting location of picking data.  

 

At each state the parameter is different, but operation is the same. 

 

I have tried to write a very long if elsif statement to achieve the operation but come with a low Fmax and high logic unit usage. Thus I want to write it in a way which only build one component with different input signals at different stage, since all the operations is the same ( pick data -> compare -> store to RAM2) but with different parameters (e.g. starting location of pick data).  

 

At each stage, I need to initialize some signals/variables in the process, but I am not sure how to do that. 

 

Or is there any better way to do this?
Altera_Forum
Honored Contributor I
79 Views

I suggest stepping away from the code, and drawing the design you expect on paper, or visio, or some diagram. Then, when you understand the circuit you expect, come back and write the VHDL. HDL is Hardware description language. If you dont know what hardware you expect, then you are unlikely to write good VHDL. 

 

Merge sorts work best with lots of data in parrallel. With two rams, you are going to take a lot of clocks reading and re-reading the values.
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