verilog code for serial in parallel out shift register

[Altera_Forum]

I have written serial in parallel out shift register verilog code. How to write the code for it without the testbench to simulate,So that data (serial input) should be continuously sent (maximum up to 4 bits i want to send). 

 module trai1enc( din ,clk ,reset ,dout ); output [2:0] dout ; wire [2:0] dout ; input [3:0] din ; input clk ; wire clk ; input reset ; wire reset ; reg [2:0]s; initial s=0; assign din[0]=1; assign din[1]=0; assign din[2]=0; assign din[3]=1; genvar i; for (i=0;i<=3;i=i+1) begin if (i==0)begin //i=0  always @ (posedge (clk)) begin   if (reset)  s <= 0;  else begin  s[2] <= din[0];  s[1] <= s[2];  s[0] <= s[1];  end end assign dout = s; end else if (i==1)begin //i=1  always @ (posedge (clk)) begin   if (reset)  s <= 0;  else begin  s[2] <= din[1];  s[1] <= s[2];  s[0] <= s[1];  end end assign dout = s; end else if (i==2)begin //i=2  always @ (posedge (clk)) begin   if (reset)  s <= 0;  else begin  s[2] <= din[2];  s[1] <= s[2];  s[0] <= s[1];  end end assign dout = s; end else begin always @ (posedge (clk)) begin //i=3  if (reset)  s <= 0;  else begin  s[2] <= din[3];  s[1] <= s[2];  s[0] <= s[1];  end end assign dout = s; end end endmodule  In above code,I have used for loop to increment index and assign next data bit,but index is not incrementing and data bits are not assigning.How do i rectify it?I wanna simulate it without test bench.

[Altera_Forum]

I don't know how to simulate without a test bench. If you refuse to write a test bench then the only other option I know of is to debug it in hardware.

[Altera_Forum]

--- Quote Start ---  I have written serial in parallel out shift register verilog code. How to write the code for it without the testbench to simulate,So that data (serial input) should be continuously sent ...  i wanna simulate it without test bench.  --- Quote End ---    Not possible. providing the simulation stimulus inputs is what a test bench does. And even better a test tench will be written to check your results are correct for the given inputs.  So you need to go back and learn / think about the logic design process using an HDL. The concept of a test bench is an integral part of this process.