I am trying to use the Qsys component editor to create an instance of one of my verilog files to use in Qsys.I have a header file (registers.vh) that has the definitions for a number of `defines that are used in the verilog file. I haven't figured out how to tell Qsys component editor where to find this file. When I try to analyze the RTL files I get the error message: Error: Verilog HDL File I/O error at meas.v(51): can't open Verilog Design File "registers.vh" File: /abaxis/engine ii/fpga/custom/meas/hdl/meas.v Line: 51 I tried adding the file to the synthesis files list but that didn't help How do I deal with this? Thanks Rod
Did you make sure to indicate that meas.v is (I presume) the top-level file? You set this in the Component Editor files tab. If you added registers.vh first, the tool might think that is the top-level file for your custom component.