verilog notes

Altera_Forum · ‎03-19-2012

please send verilog notes to write program using loop function like for ,while, etc.,

Altera_Forum · ‎03-19-2012

What if we say no?

Altera_Forum · ‎03-19-2012

Vivek,

Your inquiries are vague and broad and are asking the community to develop your Verilog code for you. If you want help from the community, I suggest you develop your code, post the information and ask community for optimization ideas.

This site is not intended to complete student homework or assignments for them.

Altera_Forum · ‎03-26-2012

module fulladder(

input a,b,c,

output sum,carry

);

wire s1,s2,a1,a2,a3;

xor x1(s1,a,b);

xor x2(sum,s1,c);

and a11(a1,a,b);

and a2(a2,b,c);

and a3(a3,a,c);

or o1(carry,a,b,c);

endmodule

its ordinary verilog progarm if we use for loop use to reduce the code length and also less time to design.i try in loop function

plz corect this program

module fa(a,b,c,sum,carry);

input a,b,c;

output sum,carry;

integer i,j;

for (i=0;i<=1;i=i+1);

xor(i) x(i)(s(i),a,b,c);

for(j=0;j<=2;j=j+1)

and(j) a(j) )carry, a,b,c);

endmodule

Altera_Forum · ‎03-26-2012

That's no valid Verilog syntax. Seems like you are just guessing. Please review a Verilog text book of your choice for the correct way to write a generate-loop statement.

Altera_Forum · ‎03-26-2012

I would avoid loops unless you are creating generate loop structures. Generated loop structures are unrolled when synthesized resulting in parallel hardware. If you were looking to use a loop to sequence your hardware I would recommend using statemachines or counters to do this.

Altera_Forum · ‎11-22-2012

you can try here vol.verilog.com