Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17268 Discussions

verilog testbench file in emacs verilog mode

Altera_Forum
Honored Contributor II
3,569 Views

The testbench templates created by quartus-II (Processing->Start->Test Bench Template Writer) produce <filename>.vt files. When I try to open them in my emacs text editor, they do not open in verilog mode. Does anyone know if there is a way to: 

 

1.) Change the default extension used by the Test Bench Template Writer to be something like, say, <filename>_tb.v 

2.) Force emacs to open a <filename>.vt file in verilog mode  

 

I've been changing the filenames manually, but this requires annoying extra steps every time I create a new test bench. 

 

Thanks!
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
2,418 Views

 

--- Quote Start ---  

 

2.) Force emacs to open a <filename>.vt file in verilog mode  

 

--- Quote End ---  

 

 

You're looking for auto-mode-alist 

 

This article looks fairly short and to the point: 

 

http://jeremy.zawodny.com/emacs/emacs-4.html
0 Kudos
Altera_Forum
Honored Contributor II
2,418 Views

It worked! That was perfect, thanks for the link.

0 Kudos
Reply