vhdl code for state machine

Altera_Forum · ‎02-01-2013

Hai,

Can anyone justify what the different between two line codes below:

1) case cycle is

when 0l1l7 =>cp<=SXT(bm,11)+b3;

end case

2) if cycle=2 or cycle=3 then

cm<=SXT(b2,11)-b3;

end if

I'm curious the function of "l". Is it it mean by "AND" function? Thanks in advance

Altera_Forum · ‎02-01-2013

| in this context is just to combine several cases in one line and avoid repeating some code.when 0|1|7 =>cp<=SXT(bm,11)+b3;is equivalent towhen 0 => cp<=SXT(bm,11)+b3; when 1 => cp<=SXT(bm,11)+b3; when 7 => cp<=SXT(bm,11)+b3;

Altera_Forum · ‎02-01-2013

IIRC, | can only be used in case statements or in with..select statements. It is not an "or" operator.

Altera_Forum · ‎02-04-2013

Hai Daixiwen and Tricky,

Thanks for your explanations. I understand now, very appreciates. :)