Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
17049 Discussions

vho generation

Altera_Forum
Honored Contributor II
‎02-16-2015 02:58 PM
1,154 Views

The .vho file, is generated with BUFFER std_logic types instead of inout type, causing a bad simulation on modelsim.  

If I change some pin assignments, the new vho is ok, but after another compilation the buffer std_logic returns for  

all the outputs an inout signals. Any idea?
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.