- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
i'am beginner in QuartusII & vhdl (& english sorry). I try to design a modul . When my 2 ram is full, i receive flag to begin "read". i read my RAM, wait busyUSB is falling, and change RAM to read too.... So unconstrained, i have violating timing in statemachine. I think that come from my design conception but i don't find my error I attached my modul in attachements. Please help and thanks polycedLink Copied
0 Replies
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page