warning: connected to dangling logic and will be removed

[Altera_Forum]

I have the output port width of 12 bits, and the intermediate result is of 14 bit width with the first 3 bits being sign bits (result of 3 addition). I need to remove the first two sign bits (no overflow) and assign the last 12 bits to the output port. However, I keep getting warning: connected to dangling logic, logic that only feeds to dangling port will be removed. How should I fix this warning?

[Altera_Forum]

That's seem pretty normal. The optimizer removes the logic required to generate the highest 2 bits in order to spare unused resources. 

The warning is supposed to make you aware of this, but it won't affect your functional behaviour.

[Altera_Forum]

So, it means I can simply ignore warnings like this. However, is there a way to remove these warnings by making some choices in the settings of Quartus II? In this way, I could make sure I didn't miss up any other important warnings?

[Altera_Forum]

You can indeed ignore such warnings, provided you are sure they don't come from actual design errors. 

Removing them is not a good practice because it makes sense they are kept there: for example, how could Quartus know if the upper 2 bits of your 14bit result have been left unconnected intentionally, or maybe because of a hdl typo ?