Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15553 Discussions

when i create simulation model,Error: An unexpected error occurred during Generate: java lang.Error:

ishikawa
Beginner
537 Views

when i create simulation model,Error: An unexpected error occurred during Generate: java.lang.Error: Call to quartus_sh failed unexpectedly: CreateProcess failed: No such file or directory

*******************************************************
i++ debug log file
This file contains diagnostic information. Any errors
or unexpected behavior encountered when running i++
should be reported as bugs. Thank you.
*******************************************************

Compiler Command: i++ -march=CycloneV counter.cpp -o test-fpga.exe

2020.10.15.14:47:24 Info: Doing: <b>qsys-script --script=count.tcl</b>
2020.10.15.14:47:27 Info: create_system count
2020.10.15.14:47:28 Info: set_project_property HIDE_FROM_IP_CATALOG false
2020.10.15.14:47:28 Info: set_project_property DEVICE_FAMILY Cyclone V
2020.10.15.14:47:28 Info: set_project_property DEVICE 5CEFA9F23I7
2020.10.15.14:47:28 Info: add_instance count_internal_inst count_internal
2020.10.15.14:47:28 Info: set_instance_property count_internal_inst AUTO_EXPORT true
2020.10.15.14:47:28 Info: save_system count.qsys
Generating qsys simulation system: tb
ys-script --1 --search-path=C:/intelFPGA_lite/17.1/hls/ip/,.,../components/**/*,$ --script=C:/intelFPGA_lite/17.1/hls/share/lib/tcl/hls_sim_generate_qsys.tcl --cmd=set quartus_pro 0; set num_reset_cycles 4; set sim_qsys tb; set component_list count; set component_call_count_filename .</b>
2020.10.15.14:47:33 Info: create_system tb
2020.10.15.14:47:33 Info: add_instance clock_reset_inst hls_sim_clock_reset
2020.10.15.14:47:33 Info: set_instance_parameter_value clock_reset_inst RESET_CYCLE_HOLD 4
2020.10.15.14:47:33 Info: add_instance count_inst count
2020.10.15.14:47:34 Info: get_composed_instance_assignment count_inst count_internal_inst hls.cosim.name
2020.10.15.14:47:34 Info: add_instance main_dpi_controller_inst hls_sim_main_dpi_controller
2020.10.15.14:47:34 Info: set_instance_parameter_value main_dpi_controller_inst NUM_COMPONENTS 1
2020.10.15.14:47:34 Info: set_instance_parameter_value main_dpi_controller_inst COMPONENT_NAMES_STR count
2020.10.15.14:47:34 Info: set_instance_parameter_value main_dpi_controller_inst SIM_COMPONENT_CALL_COUNT_LOG_FILE .
2020.10.15.14:47:34 Info: add_connection clock_reset_inst.clock main_dpi_controller_inst.clock
2020.10.15.14:47:34 Info: add_connection clock_reset_inst.clock2x main_dpi_controller_inst.clock2x
2020.10.15.14:47:34 Info: add_connection clock_reset_inst.reset main_dpi_controller_inst.reset
2020.10.15.14:47:34 Info: add_connection main_dpi_controller_inst.reset_ctrl clock_reset_inst.reset_ctrl
2020.10.15.14:47:34 Info: add_connection clock_reset_inst.clock count_inst.clock
2020.10.15.14:47:34 Info: add_connection clock_reset_inst.reset count_inst.reset
2020.10.15.14:47:34 Info: get_instance_interfaces count_inst
2020.10.15.14:47:34 Info: get_instance_interface_property count_inst call DESCRIPTION
2020.10.15.14:47:34 Info: get_instance_interface_property count_inst call CLASS_NAME
2020.10.15.14:47:34 Info: get_instance_interface_ports count_inst call
2020.10.15.14:47:34 Info: get_instance_interface_property count_inst clock DESCRIPTION
2020.10.15.14:47:34 Info: get_instance_interface_property count_inst clock CLASS_NAME
2020.10.15.14:47:34 Info: get_instance_interface_ports count_inst clock
2020.10.15.14:47:34 Info: get_instance_interface_property count_inst reset DESCRIPTION
2020.10.15.14:47:34 Info: get_instance_interface_property count_inst reset CLASS_NAME
2020.10.15.14:47:34 Info: get_instance_interface_ports count_inst reset
2020.10.15.14:47:34 Info: get_instance_interface_property count_inst return DESCRIPTION
2020.10.15.14:47:34 Info: get_instance_interface_property count_inst return CLASS_NAME
2020.10.15.14:47:34 Info: get_instance_interface_ports count_inst return
2020.10.15.14:47:34 Info: get_instance_interface_property count_inst returndata DESCRIPTION
2020.10.15.14:47:34 Info: get_instance_interface_property count_inst returndata CLASS_NAME
2020.10.15.14:47:34 Info: get_instance_interface_ports count_inst returndata
2020.10.15.14:47:34 Info: get_composed_instance_assignment count_inst count_internal_inst hls.cosim.name
2020.10.15.14:47:34 Info: add_instance component_dpi_controller_count_inst hls_sim_component_dpi_controller
2020.10.15.14:47:34 Info: add_connection clock_reset_inst.clock component_dpi_controller_count_inst.clock
2020.10.15.14:47:34 Info: add_connection clock_reset_inst.clock2x component_dpi_controller_count_inst.clock2x
2020.10.15.14:47:34 Info: add_connection clock_reset_inst.reset component_dpi_controller_count_inst.reset
2020.10.15.14:47:34 Info: add_connection component_dpi_controller_count_inst.component_call count_inst.call
2020.10.15.14:47:34 Info: add_connection count_inst.return component_dpi_controller_count_inst.component_return
2020.10.15.14:47:34 Info: get_instance_interfaces count_inst
2020.10.15.14:47:34 Info: get_instance_interface_port_property count_inst returndata returndata WIDTH
2020.10.15.14:47:34 Info: set_instance_parameter_value component_dpi_controller_count_inst RETURN_DATAWIDTH 32
2020.10.15.14:47:34 Info: add_connection count_inst.returndata component_dpi_controller_count_inst.returndata
2020.10.15.14:47:34 Info: set_instance_parameter_value component_dpi_controller_count_inst COMPONENT_NAME count
2020.10.15.14:47:34 Info: add_instance count_component_dpi_controller_bind_conduit_fanout_inst avalon_conduit_fanout
2020.10.15.14:47:34 Info: set_instance_parameter_value count_component_dpi_controller_bind_conduit_fanout_inst numFanOut 0
2020.10.15.14:47:34 Info: add_instance count_component_dpi_controller_enable_conduit_fanout_inst avalon_conduit_fanout
2020.10.15.14:47:34 Info: set_instance_parameter_value count_component_dpi_controller_enable_conduit_fanout_inst numFanOut 0
2020.10.15.14:47:34 Info: add_connection component_dpi_controller_count_inst.dpi_control_bind count_component_dpi_controller_bind_conduit_fanout_inst.in_conduit
2020.10.15.14:47:34 Info: add_connection component_dpi_controller_count_inst.dpi_control_enable count_component_dpi_controller_enable_conduit_fanout_inst.in_conduit
2020.10.15.14:47:34 Info: get_instance_interfaces count_inst
2020.10.15.14:47:34 Info: get_instance_interface_ports count_inst call
2020.10.15.14:47:34 Info: get_instance_interface_ports count_inst clock
2020.10.15.14:47:34 Info: get_instance_interface_ports count_inst reset
2020.10.15.14:47:34 Info: get_instance_interface_ports count_inst return
2020.10.15.14:47:34 Info: get_instance_interface_ports count_inst returndata
2020.10.15.14:47:34 Info: add_instance split_component_start_inst avalon_split_multibit_conduit
2020.10.15.14:47:34 Info: set_instance_parameter_value split_component_start_inst multibit_width 1
2020.10.15.14:47:34 Info: add_connection main_dpi_controller_inst.component_enabled split_component_start_inst.in_conduit
2020.10.15.14:47:34 Info: add_connection split_component_start_inst.out_conduit_0 component_dpi_controller_count_inst.component_enabled
2020.10.15.14:47:34 Info: add_instance concatenate_component_done_inst avalon_concatenate_singlebit_conduits
2020.10.15.14:47:34 Info: set_instance_parameter_value concatenate_component_done_inst multibit_width 1
2020.10.15.14:47:34 Info: add_connection concatenate_component_done_inst.out_conduit main_dpi_controller_inst.component_done
2020.10.15.14:47:34 Info: add_instance concatenate_component_wait_for_stream_writes_inst avalon_concatenate_singlebit_conduits
2020.10.15.14:47:34 Info: set_instance_parameter_value concatenate_component_wait_for_stream_writes_inst multibit_width 1
2020.10.15.14:47:34 Info: add_connection concatenate_component_wait_for_stream_writes_inst.out_conduit main_dpi_controller_inst.component_wait_for_stream_writes
2020.10.15.14:47:34 Info: add_connection component_dpi_controller_count_inst.component_done concatenate_component_done_inst.in_conduit_0
2020.10.15.14:47:34 Info: add_connection component_dpi_controller_count_inst.component_wait_for_stream_writes concatenate_component_wait_for_stream_writes_inst.in_conduit_0
2020.10.15.14:47:34 Info: save_system tb.qsys
2020.10.15.14:47:39 Info: Saving generation log to D:/count222/test-fpga.prj/verification/tb/tb_generation.rpt
2020.10.15.14:47:39 Info: Starting: <b>Create simulation model</b>
2020.10.15.14:47:39 Info: qsys-generate D:\count222\test-fpga.prj\verification\tb.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=D:\count222\test-fpga.prj\verification\tb\simulation --family="Cyclone V" --part=5CEFA9F23I7
2020.10.15.14:47:39 Info: Loading verification/tb.qsys
2020.10.15.14:47:39 Info: Reading input file
2020.10.15.14:47:39 Info: Adding clock_reset_inst [hls_sim_clock_reset 1.0]
2020.10.15.14:47:39 Info: Parameterizing module clock_reset_inst
2020.10.15.14:47:39 Info: Adding component_dpi_controller_count_inst [hls_sim_component_dpi_controller 1.0]
2020.10.15.14:47:39 Info: Parameterizing module component_dpi_controller_count_inst
2020.10.15.14:47:39 Info: Adding concatenate_component_done_inst [avalon_concatenate_singlebit_conduits 1.0]
2020.10.15.14:47:39 Info: Parameterizing module concatenate_component_done_inst
2020.10.15.14:47:39 Info: Adding concatenate_component_wait_for_stream_writes_inst [avalon_concatenate_singlebit_conduits 1.0]
2020.10.15.14:47:39 Info: Parameterizing module concatenate_component_wait_for_stream_writes_inst
2020.10.15.14:47:39 Info: Adding count_component_dpi_controller_bind_conduit_fanout_inst [avalon_conduit_fanout 1.0]
2020.10.15.14:47:39 Info: Parameterizing module count_component_dpi_controller_bind_conduit_fanout_inst
2020.10.15.14:47:39 Info: Adding count_component_dpi_controller_enable_conduit_fanout_inst [avalon_conduit_fanout 1.0]
2020.10.15.14:47:39 Info: Parameterizing module count_component_dpi_controller_enable_conduit_fanout_inst
2020.10.15.14:47:39 Info: Adding count_inst [count 1.0]
2020.10.15.14:47:40 Info: Parameterizing module count_inst
2020.10.15.14:47:40 Info: Adding main_dpi_controller_inst [hls_sim_main_dpi_controller 1.0]
2020.10.15.14:47:40 Info: Parameterizing module main_dpi_controller_inst
2020.10.15.14:47:40 Info: Adding split_component_start_inst [avalon_split_multibit_conduit 1.0]
2020.10.15.14:47:40 Info: Parameterizing module split_component_start_inst
2020.10.15.14:47:40 Info: Building connections
2020.10.15.14:47:40 Info: Parameterizing connections
2020.10.15.14:47:40 Info: Validating
2020.10.15.14:47:40 Info: Done reading input file
2020.10.15.14:47:40 Warning: tb.component_dpi_controller_count_inst.dpi_control_slaves_ready: Interface has no signals
2020.10.15.14:47:40 Warning: tb.component_dpi_controller_count_inst.dpi_control_slaves_done: Interface has no signals
2020.10.15.14:47:40 Warning: tb.component_dpi_controller_count_inst.dpi_control_stream_writes_active: Interface has no signals
2020.10.15.14:47:40 Warning: tb.component_dpi_controller_count_inst: <b>component_dpi_controller_count_inst.dpi_control_slaves_ready</b> must be exported, or connected to a matching conduit.
2020.10.15.14:47:40 Warning: tb.component_dpi_controller_count_inst: <b>component_dpi_controller_count_inst.dpi_control_slaves_done</b> must be exported, or connected to a matching conduit.
2020.10.15.14:47:40 Warning: tb.component_dpi_controller_count_inst: <b>component_dpi_controller_count_inst.dpi_control_stream_writes_active</b> must be exported, or connected to a matching conduit.
2020.10.15.14:47:40 Warning: tb.component_dpi_controller_count_inst: <b>component_dpi_controller_count_inst.read_implicit_streams</b> must be exported, or connected to a matching conduit.
2020.10.15.14:47:40 Warning: tb.component_dpi_controller_count_inst: <b>component_dpi_controller_count_inst.readback_from_slaves</b> must be exported, or connected to a matching conduit.
2020.10.15.14:47:40 Info: tb: Generating <b>tb</b> "<b>tb</b>" for SIM_VERILOG
2020.10.15.14:47:41 Info: clock_reset_inst: "<b>tb</b>" instantiated <b>hls_sim_clock_reset</b> "<b>clock_reset_inst</b>"
2020.10.15.14:47:41 Info: component_dpi_controller_count_inst: "<b>tb</b>" instantiated <b>hls_sim_component_dpi_controller</b> "<b>component_dpi_controller_count_inst</b>"
2020.10.15.14:47:41 Info: concatenate_component_done_inst: "<b>tb</b>" instantiated <b>avalon_concatenate_singlebit_conduits</b> "<b>concatenate_component_done_inst</b>"
2020.10.15.14:47:41 Info: count_component_dpi_controller_bind_conduit_fanout_inst: "<b>tb</b>" instantiated <b>avalon_conduit_fanout</b> "<b>count_component_dpi_controller_bind_conduit_fanout_inst</b>"
2020.10.15.14:47:41 Info: count_inst: "<b>tb</b>" instantiated <b>count</b> "<b>count_inst</b>"
2020.10.15.14:47:41 Info: main_dpi_controller_inst: "<b>tb</b>" instantiated <b>hls_sim_main_dpi_controller</b> "<b>main_dpi_controller_inst</b>"
2020.10.15.14:47:41 Info: split_component_start_inst: "<b>tb</b>" instantiated <b>avalon_split_multibit_conduit</b> "<b>split_component_start_inst</b>"
2020.10.15.14:47:41 Info: irq_mapper: "<b>tb</b>" instantiated <b>altera_irq_mapper</b> "<b>irq_mapper</b>"
2020.10.15.14:47:41 Info: count_internal_inst: "<b>count_inst</b>" instantiated <b>count_internal</b> "<b>count_internal_inst</b>"
2020.10.15.14:47:41 Info: tb: Done "<b>tb</b>" with 10 modules, 70 files
2020.10.15.14:47:41 Info: qsys-generate succeeded.
2020.10.15.14:47:41 Info: Finished: <b>Create simulation model</b>
2020.10.15.14:47:41 Info: Starting: <b>Create Modelsim Project.</b>
2020.10.15.14:47:41 Info: sim-script-gen --spd=D:\count222\test-fpga.prj\verification\tb\tb.spd --output-directory=D:/count222/test-fpga.prj/verification/tb/simulation/ --use-relative-paths=true
2020.10.15.14:47:41 Info: Doing: <b>ip-make-simscript --spd=D:\count222\test-fpga.prj\verification\tb\tb.spd --output-directory=D:/count222/test-fpga.prj/verification/tb/simulation/ --use-relative-paths=true</b>
Exception in thread "main" java.lang.Error: Call to quartus_sh failed unexpectedly:
CreateProcess failed: No such file or directory
------------------------------------------------
package "tb2" isn't loaded statically
while executing
"load "" tb2 "
------------------------------------------------

0 Kudos
6 Replies
ishikawa
Beginner
510 Views

I use Quartus prime lite17.1,Modelsim starter edition,intel HLS compiler.

I want to generate verilog from C++ using intel hls compiler.

EBERLAZARE_I_Intel
488 Views

Hi,

Are you using Windows or Linux?

You may need to check if your are navigated to the correct directory:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/hls/archives/ug-hls-gett...

 

You may refer to below document on the HLS compiler reference manual:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/hls/mnl-hls-std-referenc...

 

ishikawa
Beginner
478 Views

 i use windows10.

We have already checked the sites provided. I'm following, but when I do test-fpga at the command prompt, I get an error like I described in the first paragraph.

I've attached the batch file I'm using. I would be very grateful if you can find a solution.

-------------------------------------------------------------------------------------------------------------

ihc_setup.bat

 

@echo off

::Please Set Following Param
::################################################################
::Set IHC root path
set IHCROOT=C:\intelFPGA_lite\17.1\hls
::Set VC install path
set VC_INSTALL=C:\Program Files (x86)\Microsoft Visual Studio 10.0
::################################################################

::Do not edit from here!!
::################################################################
::Set Tools Env
set VS100COMNTOOLS=%VC_INSTALL%\Common7\Tools
set PATH=%VC_INSTALL%\VC\bin\amd64;C:\IntelFPGA\17.1\modelsim_ase\win32aloem;%PATH%
set INCLUDE=C:\Program Files (x86)\Microsoft SDKs\Windows\v7.1\Include;%VC_INSTALL%\VC\include;%INCLUDE%
set LIB=%VC_INSTALL%\VC\lib\amd64;C:\Program Files (x86)\Microsoft SDKs\Windows\v7.1\Lib\x64;%LIB%
set LIBPATH=%VC_INSTALL%\VC\lib\amd64;C:\Program Files (x86)\Microsoft SDKs\Windows\v7.1\Lib\x64;%LIBPATH%

call %IHCROOT%\init_hls.bat

cmd

-------------------------------------------------------------------------------------------------------------

build.bat

 

@echo off
set "SOURCE_FILES=counter.cpp"
set "HLS_CXX_FLAGS="
:: This batch file will compile the example design to three standard targets:
:: 1) test-msvc Compile the example design to the CPU
:: Uses Visual Studio 2010
:: 2) test-x86-64 Compile the example design to the CPU
:: Uses the Intel HLS Compiler
:: 3) test-fpga Synthesize the example design to HDL
:: Generates a cosimulation executable to simulate the HDL
:: Uses the Intel HLS Compiler
:: 4) clean Remove any temporary files generated by the compiler
:: Usage: build.bat <target>
:: Example: build.bat test-x86-64

:: Only one argument expected
if not "%2"=="" goto usage

:: Accept the user's target, else default to x86-64
if not "%1"=="" (
set "TARGET=%1"
) else (
set "TARGET=test-x86-64"
echo No target specified, defaulting to %TARGET%
echo Available targets: test-x86-64, test-fpga, test-msvc, clean
)

:: Any tools installed with HLS can be found relative to the location of i++
for %%I in (i++.exe) do (
set "HLS_INSTALL_DIR=%%~dp$PATH:I"
)
set "HLS_INSTALL_DIR=%HLS_INSTALL_DIR%.."

:: Set up the compile variables
if "%TARGET%" == "test-x86-64" (
set "CXX=i++"
set "CXXFLAGS=%HLS_CXX_FLAGS% -march=x86-64"
set "LFLAGS=-o %TARGET%.exe"
) else if "%TARGET%" == "test-fpga" (
set "CXX=i++"
set "CXXFLAGS=%HLS_CXX_FLAGS% -march=CycloneV
set "LFLAGS=-o %TARGET%.exe"
) else if "%TARGET%" == "test-msvc" (
set "CXX=cl"
set "CXXFLAGS=/I ""%HLS_INSTALL_DIR%\include"" /nologo /EHsc /wd4068 /DWIN32 /MD"
set "LFLAGS=/link ""/libpath:%HLS_INSTALL_DIR%\host\windows64\lib"" hls_emul.lib /out:%TARGET%.exe"
) else if "%TARGET%" == "clean" (
del /S /F /Q test-msvc.exe test-fpga.exe test-fpga.prj test-x86-64.exe > NUL
rmdir /S /Q test-fpga.prj > NUL
goto:eof
) else (
goto usage
)

:: Replace "" with " in the flags
set "CXXFLAGS=%CXXFLAGS:""="%"
set "LFLAGS=%LFLAGS:""="%"

:: Kick off the compile
echo %CXX% %CXXFLAGS% %SOURCE_FILES% %LFLAGS%
%CXX% %CXXFLAGS% %SOURCE_FILES% %LFLAGS%
if not ERRORLEVEL 0 (
echo Error: Compile failed
exit /b 1
)
echo Run %TARGET%.exe to execute the test.

:: We're done!
goto:eof

:: Dump the usage if we get unexpected input
:usage
echo Usage: build.bat [target]
echo Targets: test-msvc, test-x86-64, test-fpga, clean
echo Example: build.bat test-x86-64
exit /b 2

-----------------------------------------------------------------------------------

 

EBERLAZARE_I_Intel
429 Views

Hi,

Have you try using the version 19.3 and above to test?

ishikawa
Beginner
412 Views

I used 17.1 because I heard that there is no intelHLS compiler after 17.1.

I checked the manual and did a high-level synthesis, but I got the following error in the debug file.

---------------------------------------------------------------------------------------------------------------------

2020.11.16.15:11:40 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2020.11.16.15:11:40 Info: Finished: <b>Create Modelsim Project.</b>
Error loading design
er\test-fpga.prj\verification>set rundir=c:\hlspractice\counter\test-fpga.prj\verification

c:\hlspractice\counter\test-fpga.prj\verification>set scripthome=c:\hlspractice\counter\test-fpga.prj\verification\

c:\hlspractice\counter\test-fpga.prj\verification>cd c:\hlspractice\counter\test-fpga.prj\verification\

c:\hlspractice\counter\test-fpga.prj\verification>vsim -batch -do "do tb/simulation/mentor/msim_compile.tcl"
Reading C:/altera/13.1/modelsim_ase/tcl/vsim/pref.tcl
Error: ** Error: (vish-3296) Unknown option '-batch'.
Error: Use the -help option for complete vsim usage.

c:\hlspractice\counter\test-fpga.prj\verification>set exitCode=1

c:\hlspractice\counter\test-fpga.prj\verification>cd c:\hlspractice\counter\test-fpga.prj\verification

c:\hlspractice\counter\test-fpga.prj\verification>exit /b 1

EBERLAZARE_I_Intel
342 Views
Reply