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when i create simulation model for ip core,Error: An unexpected error occurred during Generate: java.lang.Error: Call to quartus_sh failed unexpectedly: CreateProcess failed: No such file or directory

LZezh
Novice
1,159 Views

Info: Saving generation log to D:/Project/Quartus_Project/Data_Recorder/prj/Entity_name/Entity_name_generation.rpt

Info: Starting: Create simulation model

Info: qsys-generate D:\Project\Quartus_Project\Data_Recorder\prj\Entity_name.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=D:\Project\Quartus_Project\Data_Recorder\prj\Entity_name\simulation --family="MAX 10" --part=10M08SAU169C8G

Progress: Loading prj/Entity_name.qsys

Progress: Reading input file

Progress: Adding modular_adc_0 [altera_modular_adc 16.1]

Progress: Parameterizing module modular_adc_0

Progress: Building connections

Progress: Parameterizing connections

Progress: Validating

Progress: Done reading input file

Info: Entity_name: Generating Entity_name "Entity_name" for SIM_VERILOG

Info: modular_adc_0: "Entity_name" instantiated altera_modular_adc "modular_adc_0"

Info: control_internal: "modular_adc_0" instantiated altera_modular_adc_control "control_internal"

Info: Entity_name: Done "Entity_name" with 3 modules, 8 files

Info: qsys-generate succeeded.

Info: Finished: Create simulation model

Info: Starting: Create Modelsim Project.

Info: sim-script-gen --spd=D:\Project\Quartus_Project\Data_Recorder\prj\Entity_name\Entity_name.spd --output-directory=D:/Project/Quartus_Project/Data_Recorder/prj/Entity_name/simulation/ --use-relative-paths=true

Info: Doing: ip-make-simscript --spd=D:\Project\Quartus_Project\Data_Recorder\prj\Entity_name\Entity_name.spd --output-directory=D:/Project/Quartus_Project/Data_Recorder/prj/Entity_name/simulation/ --use-relative-paths=true

Error: An unexpected error occurred during Generate: java.lang.Error: Call to quartus_sh failed unexpectedly:

CreateProcess failed: No such file or directory

------------------------------------------------

package "tb2" isn't loaded statically

  while executing

"load "" tb2 "

------------------------------------------------

 

6 Replies
Vicky1
Employee
625 Views

Hi,

This issue may occur because of Environmental variable so please refer the below solution link,

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base...

 

You can set or remove certain paths from your environment variable in windows as fallows, 

 1) Open Control Panel --> Systems --> Advanced system settings --> 'Advanced' Tab --> Environment variables--> Under System variables

2) Look for Path(QUARTUS_ROOTDIR) and click 'Edit' 

3) Either set it correct version or remove

 

please let me know how it works for you.

Regards,

Vicky

LZezh
Novice
625 Views

Very thank you,but I have been tried your solution,it didn't work.

LZezh
Novice
625 Views

When I generate ip without creating simulation model,it works fine.but when generate file for simulation, it went wrong.ip-setup-simulation and ip-make-simscript got wrong.

ishikawa
Beginner
568 Views

I had the same problem with mine. I opened the environment variable settings from the control panel and checked the quartus_rootdir and found C:\intelFPGA_lite\17.1\quartus. I don't know how to edit it.

(i use quartus prime lite17.1)

Vicky1
Employee
625 Views

Hi,

Could you provide project file for replication(Project-> Archive Project)?

 

Regards,

Vicky

Vicky1
Employee
625 Views

Hi,

Have you resolved the issue?

Should I consider that case to be closed?

 

Regards,

Vicky

 

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