why error near text "port"; expecting "(", or "'", or "."

[Altera_Forum]

Error (10500): VHDL syntax error at Transmit2.vhd(106) near text "port"; expecting "(", or "'", or "." 

Error (10500): VHDL syntax error at Transmit2.vhd(142) near text ";"; expecting ":=", or "<="    constant enableit : STD_LOGIC := '1';  constant disableit : STD_LOGIC := '0';    process(A)  begin  while (whilelooptrue = enableit) loop    if SW(0) = '1' then    H1:tether port map (     ff_tx_data => tx_data,  ff_tx_clk => CLOCK_50, --: IN STD_LOGIC;  read => disableit, --: IN STD_LOGIC;  writedata => tx_data, --: IN STD_LOGIC_VECTOR (31 DOWNTO 0);  write => enableit, --: IN STD_LOGIC;  clk => CLOCK_50, --: IN STD_LOGIC;  reset => disableit, --: IN STD_LOGIC;    tx_clk => CLOCK_50, --: IN STD_LOGIC;    set_10 => set_10_external, --: IN STD_LOGIC;  set_1000 => set_100_external, --: IN STD_LOGIC;  ff_tx_crc_fwd => enableit, --: IN STD_LOGIC;    ff_tx_rdy => enableit, --: OUT STD_LOGIC;    ena_10 => disableit, --: OUT STD_LOGIC;  eth_mode => disableit, --0 = 10/100Mbps, 1 = 1000Mbps : OUT STD_LOGIC;   ff_tx_a_full => enableit, --: OUT STD_LOGIC;  ff_tx_a_empty => disableit, --: OUT STD_LOGIC;   magic_wakeup => disableit --: OUT STD_LOGIC);  &nbsp;);  end if;  end loop;  end process;

[Altera_Forum]

A component can be only instantiated in concurrent code, not inside a process.

[Altera_Forum]

does it mean that i move H1:tether port map outside the process and at the same time assign a variable to write like this write => whetherenable, --: IN STD_LOGIC; 

 then in the process, set whetherenable to '1' when SW(0) = '1' else whetherenable to '0'

[Altera_Forum]

The component instance can be linked to the process by signals, not variables. Variables are only defined inside a process. 

 At second sight, I noticed several violations of VHDL synatax/semantic rules - while constructs aren't supported for synthesizable VHDL - you can't connect multiple output ports to the same signal

[Altera_Forum]

excellent !!! i change to use signal instead of variable outside process , it is success to pass syntax checking.