why qsys use type "logic" for inout? inouts are nets by definition, not variable.

[ARach7]

1. Qsys file “avalon_i2c_master.sv” had this illegal code (inout is a net, it cannot be typed as a variable)

inout logic sda_inout;

Such code yields this error:

      Error-[VILIOP] Variable in low conn of inout port

              Solution: manual code change, change inout type from logic to wire.

[MEIYAN_L_Intel]

Hi, In SystemVerilog RTL design, 'logic' declare can only used in: 1. All point-to-point nets. If you specifically need a multi-driver net, then use one of the traditional net types like wire 2. All variables (logic driven by always blocks) 3. All input ports 4. All output ports Multiple assignments, or mixing continuous and procedural assignments, to a SystemVerilog variable is an error, which means you will most likely see compile error. Mixing and multiple assignments is only allowed for a net. Since 'inout' is a multiple-driven net, hence you will need to declare it as 'wire'. You may refer to the link below for more information: https://www.verilogpro.com/verilog-reg-verilog-wire-systemverilog-logic/ Thanks

[ARach7]

​Thanks for detailed reply.

My point was, that your customer who is using Quartus with VCS, was claiming that he didn't chose the "logic" type for an inout at file "avalon_i2c_msater.sv".

He says it's QSYS code generation tool that did that error of using "logic" instead of wire for an inout.

Can you please check this? Or your point is that user did the error here in some configuration during his qsys session?

thanks

[MEIYAN_L_Intel]

Hi, May i have your design file? So that i can duplicate the problem. Thanks

[ARach7]

​Hi;

The customer is from mil-aero industry and his files are "top secret". I have no option to provide them.

But the code is simple:     inout logic sda_inout;

[MEIYAN_L_Intel]

Hi, May i have a simple test case that can reproduce the error? So that i can duplicate the error. Thanks.

[MEIYAN_L_Intel]

Hi, May i know any update? Thanks