Question on Interrupt Coalescencing of QAT HW 2.0 / QAT (Gen4)

[OttoChow]

I have a question on behalf of the customer who evaluates QAT of Xeon 6 (E-Core).

In the "Programmer's Guide (Intel QuickAssist Technology Hardware Version 2.0)" document (Doc# 743912), it mentions a feature named - Interrupt Coalescing.  In Section 5.1 of the document, it said that Interrupt coalescing is an optional configuration in the general section of the QAT config file.

However, there is no parameter / description for interrupt coalescing mentioned in Section 5.

Will you provide more info. how to enable / disable interrupt coalescing in the configuration file?

Thank you.

Regards,

Otto

[Ronny_G_Intel]

Hi OttoChow,

I am checking the documentation and there is not much information about how to configure Interrupt Coalescing.

Interrupt coalescing can be used to optimize the handling of interrupts generated by the QAT hardware. 

The configuration for interrupt coalescing is typically found in the QAT driver's configuration files and it should be something similar to this:

# Sample QAT Configuration File with Interrupt Coalescing

[GENERAL]

ServicesEnabled = cy

ConfigVersion = 2

# Section for each acceleration device

[SHIM]

NumberCyInstances = 1

NumberDcInstances = 0

NumProcesses = 1

LimitDevAccess = 0

# Response Arbiter Configuration

# The Response Arbiter controls how the QAT device generates interrupts.

# The following settings are for interrupt coalescing.

# 'Bank' refers to the internal response banks within the QAT device.

# 'Timer' is the time in microseconds that the arbiter will wait before generating an interrupt if the number of responses does not reach 'Count'.

# 'Count' is the number of responses that will trigger an interrupt immediately.

RespArbiterConfig = Bank:0,Timer:100,Count:32; \

          Bank:1,Timer:100,Count:32; \

          Bank:2,Timer:100,Count:32; \

          Bank:3,Timer:100,Count:32

# Interrupt Coalescing Configuration

# 'Timer' is the interrupt coalescing timer in microseconds.

# 'Tx' and 'Rx' refer to the number of requests or responses respectively

# that will trigger an interrupt immediately, bypassing the timer.

InterruptCoalescingEnabled = 1

InterruptCoalescingTimer = 100

InterruptCoalescingTx = 32

InterruptCoalescingRx = 32

Please let me know if you need more information.

Regards,

Ronny G

[OttoChow]

Thank you Ronny.

The above info. is for Out-of-Tree driver configuration file.  How about in-tree driver?  I cannot find anything related to interrupt coalescing in the QAT driver code of Linux kernel.  Certainly, I may overlook.  Need your guidance for this part.

Thank you.

Regards,

Otto 

[Ronny_G_Intel]

Hi Otto,

If we are talking about user-space then n qatlib instances are hard-coded to polling mode so interrupts are not used, and therefore no point of interrupt coalescing.

Details:

linux/user/src/vfio/qat_mgr_lib.c

cy_inst->sym.is_polled = 1;

cy_inst->asym.is_polled = 1;

dc_inst->is_polled = 1;

Setting "is_polled = 1", means that the corresponding instance should operate in polled mode. In polled mode, the driver or application actively checks (polls) the device to see if it has completed its task, rather than relying on interrupts to signal completion.

In kernel afaik it’s the opposite, i.e. interrupts are used and polling is not implemented.

Regards,

Ronny G 

[OttoChow]

Thank you Ronny.

May I draw a conclusion that the QAT device configurations available thru out-of-tree QAT driver is different from the configurations available thru Linux kernel sysfs for in-tree QAT driver?

Regards,

Otto 

[Ronny_G_Intel · Accepted solution]

Hi Otto,

Yes, QAT device configuration thru QAT out-of-tree driver is different than in-tree QAT driver.

After checking internally I can say that Qatlib does not support it. 

See the Note at the top of this section

https://intel.github.io/quickassist/PERF/design_guidelines.html?highlight=coalescing#polling-vs-interrupts

"Not all use cases support interrupt mode, and not all software packages support interrupt mode".

Regards,

Ronny G

[Ronny_G_Intel]

Hi Otto,

Did you have a chance to look into my previous post? Do you have additional questions regarding this issue?

Regards,

Ronny G