U-Boot SPL 2013.01.01 (Jan 04 2015 - 15:47:14)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 25000 KHz
CLOCK: EOSC2 clock 25000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 800 MHz
CLOCK: DDR clock 400 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 400000 KHz
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 1024 MiB
SF: Read data capture delay calibrated to 3 (0 - 7)
SF: Detected N25Q128 with page size 65536, total: 16777216
U-Boot 2013.01.01 (Jan 04 2015 - 15:53:20)
CPU : Altera SOCFPGA Platform
BOARD : Altera SOCFPGA Cyclone V Board
I2C: ready
DRAM: 512 MiB
NAND: NAND: Denali NAND controller
1024 MiB
SF: Read data capture delay calibrated to 3 (0 - 7)
SF: Detected N25Q128 with page size 65536, total: 16777216
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: mii0
Hit any key to stop autoboot: 0
NAND read: device 0 offset 0x800000, size 0x300000
3145728 bytes read: OK
NAND read: device 0 offset 0x400000, size 0x600000
6291456 bytes read: OK
NAND read: device 0 offset 0x300000, size 0x7000
28672 bytes read: OK
## Starting application at 0x1FF74524 ...
## Application terminated, rc = 0x0
## Flattened Device Tree blob at 00000100
Booting using the fdt blob at 0x00000100
Loading Device Tree to 03ff7000, end 03fff171 ... OK
Starting kernel ...
