Intel® SoC FPGA Embedded Development Suite
Support for SoC FPGA Software Development, SoC FPGA HPS Architecture, HPS SoC Boot and Configuration, Operating Systems

A10SOC uboot dts script bug

BHoey
Beginner
331 Views

Hopefully the SOC team monitors this.

 

The script that is used to create the .h file from the hps_isw_handoff files that is used to generate the pinmux/devicetree for uboot has a bug.

 

The file is here :

https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2021.07/arch/arm/mach-socfpga/qts-...

 

Line 113 ...  _PU_DRV_STRG is 5 bits.  The mask should be 0x1f.

 

This did create boot issues for us.  

 

Can someone at Intel verify and correct?

 

Thanks

 

-Brian

0 Kudos
3 Replies
IntelSupport
Community Manager
283 Views

Hello BHoey,

 

We will check your report.

Please wait for a while.

Thanks


IntelSupport
Community Manager
233 Views

Hello BHoey,

 

Thank you for reporting the mask bits problem.

We have confirmed what the mask bit should be 0x1f basd on the configuration register below.

https://www.intel.com/content/www/us/en/programmable/hps/arria-10/hps.html#topic/sfo1429890685214.ht...

We will update the script in the feture release.

 

Thanks


IntelSupport
Community Manager
201 Views

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Reply