Cannot open bsp-editor with SoC EDS Pro 19.1 on Linux

[Rleduc]

Hello all,

After having struggled for too long, I had to come here to seek for help.

I want to work on SoC-FPGA projects with Intel Arria 10 board: Terasic HAN Pilot , which for information, and in my case, requires to switch on Linux, while I always worked on windows with Cylcone V devices (I guess it's time !).

So I use Ubuntu OS 18.04 and downloaded the following :

•  Intel Quartus Prime Pro Edition Design Software 22.4 for Linux:

https://www.intel.com/content/www/us/en/software-kit/764010/intel-quartus-prime-pro-edition-design-software-version-22-4-for-linux.html? 

• - Intel SoC FPGA Embedded Developpement Suite (SoC EDS) Pro Edition Software 19.1 for Linux:

https://www.intel.com/content/www/us/en/software-kit/664578/intel-soc-fpga-embedded-development-suite-soc-eds-pro-edition-software-version-19-1-for-linux.html 

• - Arria 10 Device Support (for Quartus Pro version 22.4) than you can find here :

https://www.intel.com/content/www/us/en/software-kit/764010/intel-quartus-prime-pro-edition-design-software-version-22-4-for-linux.html 

I properly installed Quartus and Arria 10 device, and I'm able to compile project using a qsys design which includes Arria 10 HPS IP.

My problem is now, that I want to use the bsp-editor to generate uboot file (I want to boot from FPGA) as explained here :

https://www.rocketboards.org/foswiki/Documentation/UBootA10FPGABoot 

When I open bsp-editor from prompt, I have the 2 following errors in the GUI that prevents me to create a new HPS BSP :

    SEVERE: Error initializing BSP Components. Ensure the QUARTUS_ROOTDIR environment variable is set properly: "Problem getting the aliases for all known families com.altera.infrastructure.devices.DeviceDBException: Could not execute query: SELECT fam_alias.alias, fam.display_name FROM family_alias fam_alias JOIN family fam ON fam.id == fam_alias.family_id union all select name, display_name from family union all select display_name, display_name from family; com.altera.jdbcsqlite.Exception: no such table: family"
    SEVERE: Error initializing BSP Components. Ensure the QUARTUS_ROOTDIR environment variable is set properly: "Librarian is 'null'"

Also I can see the following statement after these errors in the prompt :

Caused by: com.altera.infrastructure.devices.DeviceDBEnvironmentException: /home/siame/intelFPGA_pro/22.4/quartus/common/devinfo/device.db does not exist

So we can see an issue related to the QUARTUS_ROOTDIR environment variable while it is exactly set to my "/path/to/quartus" , so I don't understand why they assume it is not set properly. Secondly, there is no device.db file in the devinfo folder.

I did already read topics on this forum about the missing device.db and installing all the devices would not help, and some fixes that seem very wobbly.

I believe this may be related with the innumerable quantity of Quartus and SoC EDS versions, for instance I had to take SoC EDS 19.1 and not more recent because 19.3 doesn't include bsp-editor command, and the latest 20.1 doesn't include DS-5 anymore which is required !! So which combination of Quartus/SoCEDS would work ? Is Quartus 22.4 stable or maybe I should go with earlier versions like 21, 20 or 19, and match it with SoC EDS version ?

Hope I can get some help !

[EBERLAZARE_I_Intel]

Hi,

Thanks for contacting Intel Forum support.

Glad your Quartus compilation was a success. I believe you have set the boot selection to FPGA in Platform Designer?

Regarding the bsp-editor, for A10 and even CV currently, we are no longer using the bsp-editor to build the A10 Bootloader.

For full compilation and the build, we always refer here for our A10 SoC Dev Kit (SD card boot):

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10#Arria_10_SoC_45_Boot_from_SD_Card

More info:

https://www.rocketboards.org/foswiki/Documentation/Arria10SoCGSRD

The boot from FPGA that you shared is very old and quite obsolete, and currently only used for reference.

Please allow me some time, to check with our internal on this particular example to boot from FPGA using flow w/o bsp-editor.

This might takes a few days in fact.

[Rleduc]

Hello EBERLAZARE_I_Intel,

Thanks for your prompt response, take the time you need for getting the feedback.

Ok, so I better understand why this could not work.

Then I should explain the whole picture. I use in my project the Intel JESD204B IP (under evaluation licence) which allows me to compile project and to use time-limited.sof FPGA programming file.

Problem with this is that I have HPS / FPGA project so I either need to :

- Reboot HPS once FPGA is programmed with .sof (which is done with boot HPS from FPGA)

- Program FPGA during the HPS boot flow (which is commonly done with .rbf file put in SD card)

So far I always used the 1st solution since we are not allowed to convert time-limited.sof to a time-limited.rbf. 

Maybe I am not aware of other solutions existing to boot HPS from Quartus programmer or anything else? Or more generally, how to test Arria 10 HPS / FPGA projects (meaning, to fully validate the functioning of FPGA and HPS parts) that include evaluation licensed IP?

Looking forward to hearing from you,

[EBERLAZARE_I_Intel]

Hi,

Thanks for the update, let me look into it further, I shall get back to you soon.

[EBERLAZARE_I_Intel]

Hi,

I am back, so boot from FPGA for new bootloader flow is currently not supported. But you are opt to use the old flow and see what you can do with the latest bootflow.

If it had worked for you, from my side, for HPS part, it needs to boot to U-boot this valids the HPS, for the FPGA you're basically programs the FPGA then it will boots the HPS after.

So you may check by enabling the bridges in U-boot then checks the FPGA addresses in U-boot.

For resets of HPS: If the HPS is reset the FPGA must be re-programmed.

Since the feature is currently not supported for our new bootloader, we may only provide best support to you for your issue.

Do you have any further questions or any questions that is still in unanswered?

[Rleduc]

Hi,

Thank you for your answer,

Sorry I'm not very familiar with bootflow manipulation, what do you mean by programming the FPGA then it will boot HPS after ? What should I do in order to get this since I understood it is not possible ? I don't see how I can use the old flow and try to implement it in the new design.

Regards

[EBERLAZARE_I_Intel]

Hi,

In theory, how the old flow partially works is that, FPGA is programmed to the board and user can be in FPGA user mode, then it will boot the HPS and you will see the U-boot.

After all steps were done in the old flow, you add the .hex of your U-boot into the OCRAM of your FPGA in the memory initialization tab and re-compile your project to get the new .sof.

Before that, you might need to edit and change the device tree and U-boot settings to match your settings when you set the HPS IP to boot from FPGA signal = enabled.

[EBERLAZARE_I_Intel]

Hi,

Would you have any top-up questions?

[EBERLAZARE_I_Intel]

Hi,

I hope that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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