I'm trying to create my own RGMII interface for the MAX 10 Development Kit.
Until now I was working with the Cyclone 10 LP Evaluation Kit, I sucesfully created an RGMII following this intel manual:
Now I wanted to adapt my project to this new MAX 10 board, but it is not working. So I guess that the RGMII PHY of this new board doesn't have the same skew configurations. I'm not able to find any information about that, in the Cyclone LP board I was able to find that for RX the delay is already implemented inside the physical chip, for Tx it's not so I used a PLL to displace the clock phase 90º.
As I don't really know where is the problem, my plan was to just try to center-align the Rx clock, and see if I start receiving something. But I can't connect a non-dedicated clock pin to the PLL, so I can't repeat the previously done for Tx.
Any ideas on how to do that? And also any idea about the skew configuration of that specific board? (It uses the Marvel 88E1111 chip).
Also the manual says that "You can achieve this with a DLL and by assigning RX_CLK to a DQS pin or promoting RX_CLK to a global or regional net if you need a small clock latency." But I don't understand what it means and I can't find almost any information about it.
Hello, sorry for my delay in answering.
I'm working with a MAX10 FPGA embeded in Intel's Development Board, this board is connected to a switch. The Ethernet interface is a custom interface inside the FPGA that uses de board RGMII. It is working in another board but not with this one. I think that the best solution will be to implement an MDIO an modify the RGMII delays, but i'm having difficulties finding the registers of the RGMII. The physical RGMII that your board uses is the 88E1111, but the datasheet is under NDA.