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MAX 10 RGMII interface - PLL input from non-dedicated clock pin

Hello,

I'm trying to create my own RGMII interface for the MAX 10 Development Kit.

 

Until now I was working with the Cyclone 10 LP Evaluation Kit, I sucesfully created an RGMII following this intel manual:

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an477.pdf

 

Now I wanted to adapt my project to this new MAX 10 board, but it is not working. So I guess that the RGMII PHY of this new board doesn't have the same skew configurations. I'm not able to find any information about that, in the Cyclone LP board I was able to find that for RX the delay is already implemented inside the physical chip, for Tx it's not so I used a PLL to displace the clock phase 90º.

 

As I don't really know where is the problem, my plan was to just try to center-align the Rx clock, and see if I start receiving something. But I can't connect a non-dedicated clock pin to the PLL, so I can't repeat the previously done for Tx.

 

Any ideas on how to do that? And also any idea about the skew configuration of that specific board? (It uses the Marvel 88E1111 chip).

 

Also the manual says that "You can achieve this with a DLL and by assigning RX_CLK to a DQS pin or promoting RX_CLK to a global or regional net if you need a small clock latency." But I don't understand what it means and I can't find almost any information about it.

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Hello Humusk, Thank you for posting in Intel Ethernet Communities. Before we proceed, let me gather the following details for me to further help you. 1. What is the model of Intel NIC card? 2. Are you designing a board and you are integrating the Intel NIC card? 3. Do you need an assistance on integration and implementation of Intel NIC card to your board? If you have questions, please let us know. Best regards, Michael L. Intel Customer Support Under Contract to Intel Corporation
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Hello Humusk, I just want to make a follow up on the following information that I requested: 1. What is the model of Intel NIC card? 2. Are you designing a board and you are integrating the Intel NIC card? 3. Do you need an assistance on integration and implementation of Intel NIC card to your board? If you have questions, please let us know. Best regards, Michael L. Intel Customer Support Under Contract to Intel Corporation
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Hello Humusk, Just making another follow up on the information that I requested. If you have questions, please let us know. Best regards, Michael L. Intel Customer Support Under Contract to Intel Corporation
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Novice
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Hello, sorry for my delay in answering.

I'm working with a MAX10 FPGA embeded in Intel's Development Board, this board is connected to a switch. The Ethernet interface is a custom interface inside the FPGA that uses de board RGMII. It is working in another board but not with this one. I think that the best solution will be to implement an MDIO an modify the RGMII delays, but i'm having difficulties finding the registers of the RGMII. The physical RGMII that your board uses is the 88E1111, but the datasheet is under NDA.

 

Thanks,

 

Gerard.

 

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Hello Humusk, Thank you for the clarifications, Regarding your inquiry, it is best if you create another thread in our FPGA topic. They should help you further with your inquiry. https://forums.intel.com/s/ If you have questions, please let us know. Best regards, Michael L. Intel Customer Support Under Contract to Intel Corporation
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Employee
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Hi , I think you might have posted this thread into the wrong community forum. This forum only covers Intel FPGA product. Our agents can only help to provide assistance with regards to FPGA product. If you have further enquiries on other Intel product, please post your question to the correct Intel Community topics from the link below: https://forums.intel.com/s/ We will then require deleting this thread from the Intel FPGA forum topic. Thank you.
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