I plan to use PLL Reconfig Intel FPGA IP (polling mode) and PLL Intel FPGA, but in my project PLL Reconfig IP cannot drive PLL IP well
I modified the M/N/C/bandwidth/charge pump of PLL Reconfig IP through the state machine in my pll_control code, and then started configuration by writing 32'h1 to address 6'h2. However, no matter how I modify the M/N/C and bandwidth registers in PLL Reconfig IP, when I read mgmt_readdata[0] at the end of the state machine, it is always 0 instead of 1. The reconfig_to_pll passed by PLL Reconfig IP never changes, the reconfig_from_pll passed by PLL never changes, and the LOCK signal of PLL is always low. Is there any reason that may cause this?
