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I’m a Radiation Effects Engineer performing a component Single Events Effects (SEE) sensitivities assessment to the part: 10CL040YU484A7G.
I would like to know the following wafer fabrication information for the mentioned part:
1. Initial Release Date and Latest revision.
2. the minimum feature size (Distance between the elements that make up the structures on a chip, commonly known as wafer node, tech node or feature size). The size of the features are measured in nanometers. A 22 nm process technology refers to features 22 nm or 0.022 µm in size. Also called a "technology node" and "process node," early chips were measured in micrometers.
3. the process technology used (Semiconductor technology, example: bipolar, MOSFET, CMOS, etc.)
Thanks.
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Hi,
Thank you for contacting Intel community.
- Do you mean release date n latest revision of the C10 LP? What do you mean by this?
- Process technology for C10 LP is 60nm.
- Any reason to know this information?
You can also refer to C10 LP website for more information.
Regards,
Aiman
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Hi,
Thank you for contacting Intel community.
- Do you mean release date n latest revision of the C10 LP? What do you mean by this?
- Process technology for C10 LP is 60nm.
- Any reason to know this information?
You can also refer to C10 LP website for more information.
Regards,
Aiman
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Hi,
thanks for the information.
The reason to know that information is because I’m a Radiation Effects Engineer performing a component Single Events Effects (SEE) assessment for a circuit board for a confidential client.
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Hi,
Apologize that I missed out the link to our webiste;
https://www.intel.com/content/www/us/en/products/details/fpga/cyclone/10/lp.html
Did you get the information needed through our website?
Regards,
Aiman
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I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

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