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Preloader uboot SPL

JBayl
Beginner
5,917 Views

Hi,

We have a custom Cyclone V board that runs vxWorks.  All boot images are coming from the  QSPI with preloader separated from uboot.  Preloader starts @ 0x0 location, u-boot @ 0x60000.

I'm not trying to have Linux work on this board but i'm currently stuck with making the pre-loader and u-boot to work.  I followed the instructions from Rocketboards for (Cycone V Soc - Boot from QSPI) using Ubuntu22.04 on a VM on how to generate the preloader and u-boot.

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10#Introduction

I managed to compile/generate the u-boot-with-spl.sfp file using the socfpga_cyclone5_qspi_defconfig in the procedure, assuming that the generated file should at least show some boot messages on the serial port. 

But at power up, our custom board isn't showing any boot messages on the serial port.  Not even garbage text.

I then tried following the Mainline u-Boot for SocFPGA procedure to create a defconfig for our custom board but it's not compiling waiting for user input/decision. 

https://www.rocketboards.org/foswiki/Documentation/MainlineUBootForSoCFPGA

So my questions are:

- can i just write the u-boot-with-spl.sfp directly to the QSPI?  Considering the system already works with pre-loader and u-boot separated.

- is there a guide on how to generate a preloader and uboot for a custom board?

- for the custom defconfig, is there document that describes what each lines in the file mean?

I am currently enrolled to Intel® SoC FPGA Basics this coming May 25th.  I'd appreciate if you can share new materials that can help me get familiarized with using embedded Linux on a Cyclone V system.

Thanks!

 

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1 Solution
Jeet14
Employee
4,893 Views

Hi Joel,


Thanks for attending teams call.

Let me know if you have any other query on this.


Regards

Tiwari


View solution in original post

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28 Replies
Kenny_Tan
Moderator
4,461 Views

Kindly note that there will be some slowness on the first reply due to the public holiday, we will get back to you as soon as possible.



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JBayl
Beginner
4,441 Views

Thanks Kenny.  I just want to update this:

 

Typo error on "I'm not trying to have Linux work on this board....".  I meant  "I'm NOW trying to have Linux..."

 

I generated the preloader and uboot binaries using bsp-editor (default settings).  I programmed the QSPI with it and the board is booting, or at least shows boot logs on its serial port.  The 2 binaries are separate files with preloader-mkpimage.bin on 0x0 and u-boot.bin on 0x60000.

I write the u-boot-with-spl.sfp on QSPI @ 0x0.

Thanks!

 

 

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Jeet14
Employee
4,399 Views

Hi,


Please follow the steps given for Booting vxWorks on Cyclone V in AN724.

This is having steps for custom preloader, preloader changes required for QSPI, creating bootable environment for QSPI.


I am checking internally if there is any newer guide with latest tool. Also, I suggest you to check with vxWorks support team on their cyclone V BSP requirement.


Regards

Tiwari


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JBayl
Beginner
4,386 Views

Hi Tiwari,

 

vxWorks is already working.  What i'm trying to do is make Linux work.

 

The link you sent is the old method.  I can generate the preloader and uboot using the altera soc eds, but i can't generate/make it work using the new method (linux/Ubuntu host system generated).

 

I managed to generate a preloader/uboot for the Cyclone V board using the new method, programmed my custom board with it, and got some logging output from the serial port.   But it's not working properly due to wrong memory size and other stuff, which i think is because i was using the defconfig of an Intel Cyclone V Development board.  So i'm currently looking into how to get a defconfig customized for my board.  Then i saw this article:

https://www.rocketboards.org/foswiki/Documentation/HOWTOCreateADevicetreeForCycloneVSoC#Required_environment

 

Will this fix my preloader/uboot issue?   At the moment, this step isn't working for me:

[]$ wget https://developer.arm.com/-/media/Files/downloads/gnu-a/10.3-2021.07/\
binrel/gcc-arm-10.3-2021.07-x86_64-arm-none-linux-gnueabihf.tar.xz

[]$ tar xf gcc-arm-10.3-2021.07-x86_64-arm-none-linux-gnueabihf.tar.xz

 

Thanks!

 

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RKath4
Beginner
4,331 Views

Thank you for the explanation. It is clear to me.

 

 

 

 

 

 

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Jeet14
Employee
4,324 Views

Hi,


Is this issue got resolved? I see multiple reply on this.

Let me know if you have any other query on this matter.


Regards

Tiwari


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JBayl
Beginner
4,308 Views

Nope. I have tried to describe where i'm stuck at, so let me know if its not clear.

 

Is there a newer guide that shows how to create customized defconfigs?

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JBayl
Beginner
4,292 Views

I found these instructions to generate a customized defconfig. 

https://www.rocketboards.org/foswiki/Documentation/HOWTOCreateADevicetreeForCycloneVSoC#Required_environment

 

But the "make socfpga_defconfig" instruction isn't working for me.  And the make my_cv_top.dtb is also not running, which i assume is because "make socfpga_defconfig" didn't run correctly.

 

I assume the instructions from this will help me generate the correct preloader/uboot.

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Jeet14
Employee
4,236 Views

Hi,


Have you done Initial Cyclone V SoC DK board setup, tools setup, and other setup before running the make socfpga_defconfig.


Please check once again from the below link-

https://www.rocketboards.org/foswiki/Documentation/HOWTOCreateADevicetreeForCycloneVSoC?elq_cid=11325872_ts1683264782276&erpm_id=12677771_ts1683264782276#Required_environment


Regards

Tiwari




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JBayl
Beginner
4,217 Views

Hi,

I don't have a Cyclone V SoC DK board, but a custom board that has a working Preloader, u-boot, fpga image, and vxworks written on the board's QSPI.  Preloader and u-boot were generated using the old method (bsp gui).

I am only trying to generate a working preloader/u-boot image following the new steps from here:

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10#Cyclone_V_SoC_45_Boot_from_QSPI

The link you sent is for creating a Device Tree, which doesn't appear to be involved in generating a pre-loader/u-boot.   Or am i wrong?

 

Here are the steps i am doing:

Using our custom SOF and handoff files, i generated the u-boot-splx4.sfp and u-boot-with-spl.sfp using the socfpga_cyclone5_qspi_defconfig.  I then programmed our custom board QSPI with the u-boot-splx4.sfp @ 0x0.  The board's bootlog shows this error:

U-Boot SPL 2022.10-24687-g61ae22e548-dirty (May 05 2023 - 11:11:06 +0100)
DDR: Warning: DRAM size from device tree (1024 MiB)
mismatch with hardware (0 MiB).
DDR: Error: DRAM size from device tree is greater
than hardware size.
### ERROR ### Please RESET the board ###

 

Programming the QSPI with u-boot-with-spl.sfp shows the same error log.

I am guessing my error is using the socfpga_cyclone5_qspi_defconfig.  If it is, is there a guide on how to edit/customize it?

 

Thanks!

 

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Jeet14
Employee
4,088 Views

Hi,


Can you send the screenshot of your u-boot-board.dtsi file.

How much size you are having for DDR on your board, and the range configured in u-boot-board.dtsi file?


Regards

Tiwari


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JBayl
Beginner
4,065 Views

Hi Tiwari,

 

Screenshot of the socfpga_cyclone5.dtsi below.   I assume this is what you're looking for because i don't see u-boot-board.dtsi on my arch/arm/dts directory. 

I can't find dtsi mentioned on the rocketboards post.  I also don't see the dts getting considered when generating preloader/u-boot on the Cyclone5 steps.  Although i see the dts directory getting accessed on the Arria5 steps:

cd $TOP_FOLDER/a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga
./arch/arm/mach-socfpga/qts-filter-a10.sh \
../../../hps_isw_handoff/hps.xml \
arch/arm/dts/socfpga_arria10_socdk_qspi_handoff.h

My custom board has a 4GB DDR3L memory.

JBayl_1-1683796807700.png

 

Thanks!

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Jeet14
Employee
3,964 Views

Hi, 


Please add below links in your socfpga_cyclone5.dtsi 

memory@0 {

device_type = "memory";

reg = <0x0 0x40000000>;

};


Regarding preloader for cyclone V, you need to use the bsp-editor from platform design. Please refer below links for creating custom preloader for cyclone V.

https://github.com/sahandKashani/SoC-FPGA-Design-Guide/blob/master/DE1_SoC/SoC-FPGA%20Design%20Guide/SoC-FPGA%20Design%20Guide%20%5BDE1-SoC%20Edition%5D.pdf

https://community.intel.com/t5/FPGA-Wiki/ASDF-Hands-On-SoC-Bare-Metal-Demo/ta-p/735146


Regards

Tiwari




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Jeet14
Employee
3,940 Views

Hi,


Let me know if you have any query on this.


Regards

Tiwari


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JBayl
Beginner
3,910 Views

I still get 0MB RAM size. 

I edited the dtsi file before running the python script from this step:

cd $TOP_FOLDER/cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/arch/arm/mach-socfpga/cv_bsp_generator
python cv_bsp_generator.py -i $TOP_FOLDER/cv_soc_devkit_ghrd/hps_isw_handoff/soc_system_hps_0 \
-o ../../../../board/altera/cyclone5-socdk/qts

Note again that i'm not using the Cyclone V development board but our own custom board and FPGA source.

 

Boot Log:

U-Boot SPL 2022.10-24687-g61ae22e548-dirty (May 18 2023 - 15:13:00 +0100)
DDR: Warning: DRAM size from device tree (1024 MiB)
mismatch with hardware (0 MiB).
DDR: Error: DRAM size from device tree is greater
than hardware size.

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JBayl
Beginner
3,932 Views

Still working on it.  I see that the socfpga_cyclone5.dtsi gets accessed when i run make uboot (got a syntax error initially and i got prompted about it).  Fixed the syntax error but the resulting binaries aren't working.  No boot log.

 

The 2 links you sent are still using the old method (bsp-editor), so i don't feel inclined to follow that at the moment since Rocketboard's procedure shows SoC EDS will be discontinued.

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Jeet14
Employee
3,791 Views

Hi,


Any update on the issue.


Regards

Tiwari


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JBayl
Beginner
3,776 Views

Nope, i'm still stuck.  Any updated procedure or reading materials or training suggestions from Intel?

Something similar to this link from Youtube but runs through the new steps?

https://www.youtube.com/watch?v=vS7pvefsbRM&t=245s

 

 

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Jeet14
Employee
3,711 Views

Hi,


I am checking with engineering team on the latest tool user guide, training material if available I will update you ASAP.


Regards

Tiwari


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JBayl
Beginner
3,696 Views

Thanks Tiwari.

 

I attended the Intel SoC FPGA lecture.  I was able to do the lab work but it wasn't clear to me how to execute the procedure for a custom board.

It looks like I'm missing a lot when executing these steps:

Configure and build U-Boot:

cd $TOP_FOLDER/cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga
export CROSS_COMPILE=arm-none-linux-gnueabihf-
make socfpga_cyclone5_qspi_defconfig
make -j 48

Do you have a tutorial on how to edit/copy/customize a _defconfig file?

What part of this sequence gets the files generated by cv_bsp_generator.py?

 

Thanks

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