Running bare-metal from SDRAM memory. Error

[AJama4]

I am using De1-SoC board. Cyclone V (Cortex-A9). As far as I understand the base address of the SDRAM memory in the MPU address space is 0x00100000 and the ending address is 0xC0000000 by default. Its written in the TR-manual in the system interconnect chapter. My question is why am I getting an error when I try to load a simple program to the SDRAM memory with following scatter file configuration?

SDRAM 0x00100000 0x02000000 ;

{

APP_CODE + 0

{

* (+ RO , + RW , + ZI )

}

ARM_LIB_STACKHEAP 0x000800000 EMPTY 0x000100000 ; Application heap and stack

{ }

}

ERROR:

ERROR(CMD16-TAD11-NAL22): 

! Failed to load "HelloWorldARM.axf"

! Failed to write 3,132 bytes to address S:0x00100000

! General error on memory or register access.

One reason could be that the SDRAM is not configured but I am already running a preloader before loading my bare-metal program. Any hints??

[EBERLAZARE_I_Intel]

Hi,

During the preloader, did you see the SDRAM calibrated successfully?

It should look something like this:

CALIBRATION PASSED

SDRAM: 1024 MiB

Regards

[AJama4]

Hi,

Following appears in the SERIAL TERMINAL:

U-Boot SPL 2013.01.01 (Jul 01 2019 - 14:31:08)

BOARD : Altera SOCFPGA Cyclone V Board

CLOCK: EOSC1 clock 25000 KHz

CLOCK: EOSC2 clock 25000 KHz

CLOCK: F2S_SDR_REF clock 0 KHz

CLOCK: F2S_PER_REF clock 0 KHz

CLOCK: MPU clock 800 MHz

CLOCK: DDR clock 400 MHz

CLOCK: UART clock 100000 KHz

CLOCK: MMC clock 50000 KHz

CLOCK: QSPI clock 400000 KHz

RESET: COLD

INFO : Watchdog enabled

SDRAM: Initializing MMR registers

SDRAM: Calibrating PHY

SEQ.C: Preparing to start memory calibration

SEQ.C: CALIBRATION PASSED

SDRAM: 1024 MiB

ALTERA DWMMC: 0

Card did not respond to voltage select!

spl: mmc init failed: err - -17

### ERROR ### Please RESET the board ###

[EBERLAZARE_I_Intel]

Hi,

The initial error is is from the SDRAM memory controller not being configured properly during preloader.

Looking at the error of the log:

Card did not respond to voltage select!

spl: mmc init failed: err - -17

You are using SD card to boot the board? If yes, may I know the part number?

Regards.

[AJama4]

I am not using the SD Card instead, I am using DS5 debugger to load the preloader.

I was using the standard preloader of GHRD that was included with the board support package. How can I change the preloader to configure it properly?

Regards,

[EBERLAZARE_I_Intel]

Hi,

To generate and compile the preloader I highly recommend you check here (For Cyclone V), in Procedure tab there are also Screenshots of the procedure for your reference to guide you better:

https://rocketboards.org/foswiki/Documentation/GSRDPreloader

In general, you could also check other topics/tasks for Cyclone V such as compiling the Hardware Design etc.:

https://rocketboards.org/foswiki/Main/GettingStarted

From above link, choose your board, Cyclone > then your Quartus Version > Task you interested in.

[AJama4]

I have generated two separate preloaders for two separate Quartus projects but in the end the serial terminal's output is the same when I try to load the preloader using DS5 debugger.I think I didn't ask my question clearly. My question is, if its not working with the standard GHRD preloader for the De1-SoC board, then how can I change the settings or what additional should I do? I know already the whole procedure how to generate the preloader using BSP-editor and its various options.

[EBERLAZARE_I_Intel]

Hi,

Assuming you have generated the preloaders correctly;

1) Can you check the BSEL pins of the board if they have been set properly?

[AJama4]

Hello,

BSEL switch is absent so the setting is the default one by Terrasic.

[EBERLAZARE_I_Intel]

Hi,

Can you load the preloader first to make sure the SDRAM has been calibrated successfully? Only then you are to create and apply the scatter file, since the SDRAM has been brought up from preloader.

Replying back to your first posts, can you direct me to the TR-manual which demonstrate the scatter file that you mentioned?

This is the link to locate the bare metal application in the SDRAM by creating a new scatter file, is this the examples you tried to follow?:

https://www.intel.com/content/www/us/en/programmable/documentation/lro1424280108409.html#lro1424311442722

[AJama4]

Hi,

The scatter file was being written by me after reading the default SDRAM base address (starting) and ending address in MPU address space. I am first loading the preloader and then trying to run the bare-metal.

I have already followed the aforementioned example and its not working.

After, making some changes, now my preloader works fine without error; but still the bare.metal program doesn't load from the SDRAM.

Here is the output in the terminal (for preloader):

U-Boot SPL 2013.01.01 (Aug 27 2019 - 08:37:10)

BOARD : Altera SOCFPGA Cyclone V Board

CLOCK: EOSC1 clock 25000 KHz

CLOCK: EOSC2 clock 25000 KHz

CLOCK: F2S_SDR_REF clock 0 KHz

CLOCK: F2S_PER_REF clock 0 KHz

CLOCK: MPU clock 925 MHz

CLOCK: DDR clock 400 MHz

CLOCK: UART clock 100000 KHz

CLOCK: MMC clock 50000 KHz

CLOCK: QSPI clock 370000 KHz

RESET: COLD

SDRAM: Initializing MMR registers

SDRAM: Calibrating PHY

SEQ.C: Preparing to start memory calibration

SEQ.C: CALIBRATION PASSED

SDRAM: 1024 MiB

SDRAM: Ensuring specified SDRAM size is correct ...passed

SDRAM: Running EMIF Diagnostic Test ...Passed

[AJama4]

Have you tested the example you mentioned on any De1-SoC Board?

[EBERLAZARE_I_Intel]

Hi,

I did the example a month ago, followed all the steps and able to see the entry points stops at the point of the scatter file which was 0x02000000, 

Can you edit you scatter file to this:

SDRAM 0x02000000 0x02000000 ;

{

APP_CODE + 0

{

* (+ RO , + RW , + ZI )

}

ARM_LIB_STACKHEAP 0x03000000 EMPTY 0x0x01000000 ; Application heap and stack

{ }

}

[AJama4]

Hi,

I have run the Hello World program (compiled through ARM Compiler 5) with a debugger script as well as through first running the preloader by importing it and then running bare-metal program, in both cases it doesn't work.

Here is the output in Commands tab when I run the preloader in DS5;

______________________________________________________________________________________________________________

Connected to running target Altera - Cyclone V SoC (Single Core) on TCP:localhost

Stopping running target Altera - Cyclone V SoC (Single Core) on TCP:localhost on connection

Execution stopped in SVC mode at S:0x00002FA8

S:0x00002FA8  TST     r1,#4

cd "C:\Users\stable\Documents\DS-5 Workspace"

Working directory "C:\Users\stable\Documents\DS-5 Workspace"

Execution stopped in SVC mode at S:0x00002FA8

S:0x00002FA8  TST     r1,#4

source /v "C:\altera\16.0\embedded\ds-5\sw\debugger\configdb\Scripts\altera_target_check.py"

No SYSID registers could be found. Has a peripheral description file been supplied?

load "C:\Users\stable\Documents\Quartus_Workspace\01_DE1-SoC_Computer\verilog\software\spl_bsp\uboot-socfpga\spl\u-boot-spl"

Loaded section .text: S:0xFFFF0000 ~ S:0xFFFF7D4B (size 0x7D4C)

Loaded section .rodata: S:0xFFFF7D4C ~ S:0xFFFFA104 (size 0x23B9)

Loaded section .data: S:0xFFFFA108 ~ S:0xFFFFAFDB (size 0xED4)

Entry point S:0xFFFF0000

set debug-from *$ENTRYPOINT

start

Starting target with no symbolic information loaded

wait

Execution stopped in SVC mode at S:0xFFFF0000

S:0xFFFF0000  B       {pc}+0x70 ; 0xffff0070

Run

Starting target with no symbolic information loaded

Pause 1s

Interrupt

Quit

Execution stopped in UND mode at S:0xFFFF0004

S:0xFFFF0004  LDR     pc,[pc,#20] ; [0xFFFF0020] = 0xFFFF0020

Disconnected from stopped target Altera - Cyclone V SoC (Single Core) on TCP:localhost

______________________________________________________________________________________________________________

And here is the output when I run bare-metal program;

______________________________________________________________________________________________________________

Connected to stopped target Altera - Cyclone V SoC (Dual Core) on TCP:localhost

cd "C:\Users\stable\Documents\DS-5 Workspace"

Working directory "C:\Users\stable\Documents\DS-5 Workspace"

Execution stopped in UND mode at S:0xFFFF0004

S:0xFFFF0004  LDR     pc,[pc,#20] ; [0xFFFF0020] = 0xFFFF0020

source /v "C:\altera\16.0\embedded\ds-5\sw\debugger\configdb\Scripts\altera_target_check.py"

No SYSID registers could be found. Has a peripheral description file been supplied?

loadfile "C:\Users\stable\Documents\DS-5 Workspace\HelloWorldARM\Debug\HelloWorldARM.axf"

ERROR(CMD16-TAD11-NAL22):

! Failed to load "HelloWorldARM.axf"

! Failed to write 3,132 bytes to address S:0x02000000

! General error on memory or register access.

set debug-from main

start

WARNING(CMD399-COR168):

! Failed to start the target

! No function named "main" could be found

WARNING(CMD407): Trying the entry point instead

ERROR(CMD426): Cannot find symbol to start or entrypoint, the file or load commands may be used to set the entrypoint

wait

Target Message: Could not determine target state

Target Message: Could not determine target state

[AJama4]

I should mention that using the same preloader, I am able to run the program compiled through Altera Bare-metal GCC toolchain from SDRAM using the cycloneV-dk-oc-ram-hosted.ld script.

[EBERLAZARE_I_Intel]

Hi,

Seems that the SDRAM calibration is successful.

Was there any error when loading the bare metal application? Is the bare metal program a "Hello World" as in the example or your own?

Can you share the log when loading the bare metal application?

[ESaiv]

Hi. I am having this identical issue. Were you able to resolve it? I can appreciate that this was some time ago.