Im using cyclone V Soc evb board and Im trying to build example design for the ddr3 hard ip.
we are using quartus version 18.1.
memory clk: 400Mhz.
ddr interface data width:32bits
multiport: using only one port of 128bits.
pll ref clk = 100Mhz.
my question is about the clocks used for the avalon bus.
when I'm synthesizing the example design I can see that it catches 2 pll's:
1)pll for the hard ip that generates the 400Mhz, halfclk-200Mhz and some more clocks..
2)pll for the avalon bus + multiport fifos: that generates only 100Mhz.
the consumption was that the avalon bus will use the half clk rate = 200Mhz.
so if Im moving on DDR bus 32 bits( and its double rate so actually 64 bits) and from the avalon side we will move 128 bits on the multiport it will be in half rate(200Mhz).
but instead of using the 200Mhz for the avalon bus it uses the 100Mhz from the other pll and it doesnt make sense to me.
please explain to me why is that happening?
and if its ok, so why its ok?
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