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The release notes of TBB indicate that the supported hardware is the Intel Pentium 4 processor family and higher (or non-Intel processors compatible with these).
We distribute our application on the Web, and we need to detect at run-time if our application is running on a supported Intel or AMD processor, and then enable or not the usage of TBB features. We currently plan to use the CPUID instruction to detect the CPU at run-time.
1. Is there another recommended method to do this detection at run-time, or is there any service that is already provided in the TBB library?
2. What does "Pentium 4 processor family and higher" means? What is the list of processor families on which TBB can run without problem?
Thanks
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I can answer question two. It means any processor that supports the SSE2 instruction set or better.
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Would you care to elaborate?
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Search the Intel site and AMD site for archetectural programmer's reference manuals containing CPUID.
Google: CPUID eax ebx ecx edx format:.pdf site:intel.com
The CPUID instruction is issued with an index in eax (and optionally additional register) and on return, returns in eax, ebx, ecx and edx the requested information. Many of the indexes of CPUID return the same content on Intel and AMD processors. And many indexes do not (or content has different bit positions). With regards to SSE support the index and bit positions are the same
Issue CPUID with eax = 1
return registers
edx bit 25 = SSE
edx bit 26 = SSE2
ecx bit 0 = SSE3
ecx bit 9 = SSSE3
ecx bit 19 = SSE4.1
ecx bit 20 = SSE4.2 (Intel only, reserved AMD)
Both Intel ICC and MS VC++ have intrinsic function to issue/return CPUID. g++ you will have to write your own function.
Jim Dempsey
Google: CPUID eax ebx ecx edx format:.pdf site:intel.com
The CPUID instruction is issued with an index in eax (and optionally additional register) and on return, returns in eax, ebx, ecx and edx the requested information. Many of the indexes of CPUID return the same content on Intel and AMD processors. And many indexes do not (or content has different bit positions). With regards to SSE support the index and bit positions are the same
Issue CPUID with eax = 1
return registers
edx bit 25 = SSE
edx bit 26 = SSE2
ecx bit 0 = SSE3
ecx bit 9 = SSSE3
ecx bit 19 = SSE4.1
ecx bit 20 = SSE4.2 (Intel only, reserved AMD)
Both Intel ICC and MS VC++ have intrinsic function to issue/return CPUID. g++ you will have to write your own function.
Jim Dempsey
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Thank you very much for you help.
And yes, the available intinsic is helpful too.
We also concluded that we could probably test for the presence of more than one logical processor (either in multiple cores or multiple packages), and that could be enough to conclude that TBB will be runnable, and also that it is worthy to use it.
Thanks again.
And yes, the available intinsic is helpful too.
We also concluded that we could probably test for the presence of more than one logical processor (either in multiple cores or multiple packages), and that could be enough to conclude that TBB will be runnable, and also that it is worthy to use it.
Thanks again.

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