Memory Management

[Anonymous]

Hello,

Can you explain me how to treat RAM as single pointeur (flat model) without use paging in IA-32e mode, i see on Volume 3A: System Programming Guide, Part 1, we can do this :

"System architecture supports either direct physical addressing of memory or virtual memory (through paging)".

And another thing, is right that moving data are slowing by this mechanic of managed memory ? i ask this because i wonder why NVDIA can show 32M voxels (fire) in real time.

[Anonymous]

I work whitout OS: WIndows, linux, it's with my own bootloader + kernel in assembler x86/x64

[jimdempseyatthecove]

If at CPU boot time you stay in Real Mode. that is you do not switch to V86 mode nor switch to Protected mode, you can program the Descriptors used by DS and ES (FS and GS too if you want), to have Granularity of Large, Base of 0 and size of (max value). Then you can use address override prefixes to provide for full 32-bit data access though your instruction space is limited to 1MB (less I/O space).

It has been 22 years since I have done this. In fact at one time I produced and sold a product called BCCx32 that would use the Borland C++ compiler to produce a .ASM output file, then a post processor that parsed the .ASM file to convert all huge pointers into 32-bit flat pointers in the production of a new .ASM file. The converted .ASM file was compiled by Borland Turbo Assembler then linked and run under Real Mode DOS 6.22. This also require a hook for the driver for XMM. The standard XMM driver would clobber the granularity so the hook had to save and restore the granularity of the Selectors. The process was easy to use:

bccx32 foo.cpp

td foo

(yes you could use the Turbo Debugger too)

I suppose this product could be resurrected for use on Quark and Atom for situations were the code is small but data requirements are large.

Jim Dempsey

[Anonymous]

Hi, i talk about 64 bit mode :p

Well, finaly i think it's impossible, because i see on 4.5 IA-32E PAGING of Volume 3A: System Programming Guide, Part 1 that:

"With IA-32e paging, linear address are translated using a hierarchy of in-memory paging structures located using the contents of CR3.
IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.
Although 52 bits corresponds to 4 PBytes, linear addresses are limited to 48 bits; at most 256 TBytes of linear-address space may be accessed at any
given time."

But why the restriction of 48-bit linear addresses ?

And is this restriction of addressing memory is cause of the hierarchy of in-memory paging structures in IA-32e mode, or for it's for help devellopers for do multitasking.

Thanks

[jimdempseyatthecove · Accepted solution]

You still have not qualified as if your app can run "stand alone" as a Hybrid Real Mode program.

In Real Mode, you may be able to employ the trick used by BCCx32.

That set the descriptor for the selector used by DS and ES to granularity large (there may now be an even larger setting than large), and the base to 0 and size the max value (~0). Then (untested/unknown) in addition of using the address override prefix as used by BCCx32, you use the VEX prefix, thus providing 64-bit register usage in your address calculations.

This may provide you with small code access to extremely large memory without the use of a page table.

Jim Dempsey

[Anonymous]

Sound like hack, but seem too complicated ^^

Anyway it's fine to access to > 4Go but i want to use register offer by IA-32e mode, rax, rbx, r8, r15, xmm0 -> xmm15.

Nice program quickthread

[Bernard]

>>>But why the restriction of 48-bit linear addresses ?>>>

Probably CPU only supports 48-bit out of 64-bit of memory space.

http://www.codemachine.com/article_x64kvas.html

[Anonymous]

So it's the technology cause ? and in future this issues will be resolved or will be still like this ?

I see on wikipedia, 64 bit processor is aged of 13yo (Itanium: 29 may 2001).

[Bernard]

shaynox s. wrote:

So it's the technology cause ? and in future this issues will be resolved or will be still like this ?

I see on wikipedia, 64 bit processor is aged of 13yo (Itanium: 29 may 2001).

Probably there is no need to fully support on CPU 2^64 bit addressable memory space.

[Anonymous]

Except, the limit of freedom for addressing any data at any time, and cause a page fault exception cause a reset of CPU if we want to force this forbidden access memory not like in IA-32 mode (32 bit) :/