Support for AMD CPUs without mfence

[Dave_Harris]

Are old AMD CPUs without mfence supported by TBB 4.0? I gather they weren't with v2.2. According to the forum, there is a workaround that involves recompiling using a different instruction. I am hoping that by now the workaround as been incorporated into the main product. All the discussion I've found about this was a couple of years old. The documentation does not have anything relevant under "known issues", nor can I see

If not, does anyone know if Microsoft's PPL has the same limitation?

dharris@serif.comAm

[SergeyKostrov]

Quoting Dave Harris

Are old AMD CPUs without mfence supported by TBB 4.0?

[SergeyK] It looks like no. Take a look at:

windows_ia32.h
...
#define __TBB_full_memory_fence() __asm { __asm mfence }
...

As you can see there are no any CPU-related macros around __TBB_full_memory_fence for 32-bit Windowsplatforms.

Take a look atwindows_intel64.h. In thatcasefor64-bit Windows platforms__TBB_full_memory_fence depends on
a C++ compiler, that is, Intel or Microsoft.

Best regards,
Sergey

[RafSchietekat]

You mean AMD CPUs now have mfence but at some point didn't? When was that?

As a workaround, reimplement __TBB_full_memory_fence in include/tbb/machine/windows_ia??.h to, e.g., do a compare-and-swap on a global dummy variable (no loop, just a single call), or anything your compiler provides that will do the trick (built-in, new C++ standard, ...).

[SergeyKostrov]

Quoting Raf Schietekat

You mean AMD CPUs now have mfence but at some point didn't? When was that?..

It gets confusing... Take a look at adiscussion:

https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences

...There are still platforms where MFENCE is clear winner (older AMD processors, for instance)...

I think a question to AMD could clear it.

[RafSchietekat]

Consider me confused. :-)

Feel free to amend my suggestion to use a local variable instead (and/or a different RMW instruction).

[Vladimir_P_1234567890]

Hello Dave,

There are no plans to support processorsmore than 10 years old. The current HW requirements are

• Intel Pentium 4 processor family and higher
• Non Intel processors compatible with the above processors

In case there will be submitted a working patch with workaround for processors without mfence support we can consider to integrate it to the sources for open source releases

thanks

--Vladimir

[SergeyKostrov]

Quoting Sergey Kostrov

Quoting Raf Schietekat

You mean AMD CPUs now have mfence but at some point didn't? When was that?..

It gets confusing... Take a look at adiscussion:

https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences

...There are still platforms where MFENCE is clear winner (older AMD processors, for instance)...

I think a question to AMD could clear it.

I've contacted AMD and this is their response:

...
We at Global Customer Care would not be suited to answer these questions. I suggest that you visit our developer
forums and register there and post these questions you have. The correct people within the forums will give you
the best proper answer.

http://developer.amd.com/pages/default.aspx
...

[Dave_Harris]

Quoting Vladimir Polin (Intel)

There are no plans to support processors more than 10 years old.

Thanks for the reply. Although it's not what I wanted to hear, as my employer does need to support customers with old hardware.

[SergeyKostrov]

Quoting Dave Harris

Quoting Vladimir Polin (Intel)

There are no plans to support processors more than 10 years old.

Thanks for the reply. Although it's not what I wanted to hear, as my employer does need to support customers with old hardware.

Could you follow a link:

http://developer.amd.com/pages/default.aspx

fromaPost #10? Your problem is related to AMD CPUs andI thinkAMD engineers could answerall your questions.

[RafSchietekat]

Regardless of whether transparent support exists, is it not possible to apply the suggested workaround?

Another alternative, specific to Windows, seems to be MemoryBarrier(). (Hopefully "It may also prevent the compiler from re-ordering read and write operations.", my emphasis, is just bad technical writing.)

[SergeyKostrov]

>>...Regardless of whether transparent support exists, is it not possible to apply the suggested workaround? . I simply wanted to follow up. So, some time ago I've submitted a question related to the subject of our thread on three AMD's forums. Unfortunately, I didn't hear anything from AMD software / hardware engineers. Here is a summary: . ...http://forums.amd.com/forum/messageview.cfm?catid=12&threadid=160909&enterthread=y ...No responses . ...http://forums.amd.com/forum/messageview.cfm?catid=383&threadid=160956&enterthread=y ...No responses . ...http://forums.amd.com/forum/messageview.cfm?catid=13&threadid=160955&enterthread=y ...There is one response: . If I had to guess, I'd say that Athlon 64 and up probably support the instruction that you're asking about. I can only give a probably, but it's something. I tried a web search, this is what I found, and maybe it will help: https://lkml.org/lkml/2008/1/2/350 https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences http://en.wikipedia.org/wiki/Memory_ordering From what I can tell, even though at least since Athlon and Phenom, AMD did support this instruction (probably even earlier too), but it's not ideal on their CPUs. Maybe if AMD's CPU/NB frequency is brought up significantly, it'd work better.