Cyclone 10 GX Dev Kit Illegal pin error in setting up DDR3

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Cyclone 10 GX Dev Kit Illegal pin error in setting up DDR3

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I am trying to use a ping-pong phy to give access to both my nios subsystem and fpga fabric to the on board ddr3 modules. However, during compilation time I am getting illegal pin assignments as seen in the picture below.

I checked the document "External Memory Interface Pin Information for Cyclone® 10 GX Devices" - (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-10/cyclone10gxemif.pdf) and I am assigning my pins to legal control pins so what is wrong?

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