Is it possible to change the Backlight PWM frequency in Core Ultra 155H?

[Xyon]

I have a Lenovo Yoga 9i (2024) 14IMH9 with a Core Ultra 155H processor. I figured out that the screen it uses is a Samsung ATNA40YK20-0 display panel. I have realized that I frequently get headaches after using the laptop for more than an hour. I believe this is due to the low PWM frequency it uses for screen dimming, which according to online reviews is 240Hz (The Flicker Meter app on my phone shows an even lower frequency of between 100-140Hz, which matches my experience more).
I have linux (with i915 driver) installed on it and want to increase this backlight PWM frequency.

Below is the research I've done so far:
I know this was possible to do in older processors:
1. https://wiki.archlinux.org/title/Backlight#Backlight_PWM_modulation_frequency_(Intel_i915_only)
2. https://127001.me/post/eliminate-backlight-flicker-with-i915/
There are references to this Backlight PWM register, for example SBLC_PWM_CTL2 in Skylake (https://cdrdv2.intel.com/v1/dl/getcontent/685882) or SBLC_PWM_FREQ in Alchemist/Arctic Sound-M (https://cdrdv2.intel.com/v1/dl/getcontent/774482).
But the architecture and registers have significantly changed in Core Ultra and such specific backlight PWM control register is missing in its documentation (https://edc.intel.com/content/www/us/en/design/publications/14th-generation-core-processors/) although a reference to the eDP BKLTCTL signal exists in the datasheet (https://cdrdv2.intel.com/V1/DL/GETCONTENT/792044).

When I run intel_reg read 0xC8254 on my machine, it just returns 0x0. And writing to this register updates the register value but doesn't seem to change the actual backlight PWM fequency, at least based on my Flicker Meter phone app. Same is the case with 0xC8250 (Legacy Backlight Control) and 0xC8258 (Legacy Backlight Duty Cycle). They both are 0x0 and writing to them updates their values but doesn't actually change anything.


1. There is a PWMC register in the GPIO registers in the Core Ultra documentation, but is it related to the backlight PWM?
2. Getting the PWMC register's address needs the SBREG_BAR base address, which is in the P2SB registers at 00.1f.1. However, the whole P2SB block is hidden and doesn't show up with lspci/chipsec or even with RU.EFI in UEFI Shell. ChatGPT says its 0xE0000000. Can you please confirm the SBREG_BAR base address for this processor?
3. Broadly is it possible to change the eDP backlight PWM for the Core Ultra 155H and if so what is the right register?
4. Alternatively, if the 0xC8254 address is correct (and is 0 because it is not being used), is my display using the DPCD AUX input to specify the backlight PWM instead? And if so, is there a way to read/write to this DPCD AUX channel?

Thanks!

[ArchieD_Intel]

Hi Xyon,

Thank you for reaching out to the Intel Community Forum. To assist us in investigating the issue, please provide the following details:

• Have you confirmed the PWM frequency of the Samsung ATNA40YK20-0 display panel through any official documentation or manufacturer specifications, aside from the Flicker Meter app and online reviews?
• Are there any specific configurations or settings within the i915 driver that might allow for adjustment of the backlight PWM frequency on your Linux system?
• When you attempt to write to registers like 0xC8254, 0xC8250, and 0xC8258, do you receive any error messages or logs that might indicate why the changes aren't affecting the PWM frequency?

If you have any questions, please let us know. Thank you. 

Best regards,

Archie D.

Intel Customer Support Technician

[Xyon]

Thank you for your reply Archie,

• I wasn't able to find any official documentation / manufacturer specifications for this panel. Which is why I want a way to check the actual pwm frequency currently being used for my display by running the appropriate command - on linux/windows/uefi shell whichever is available. The low frequency pwm flicker is visible in both windows and linux. In any case, here are the references to the 240Hz frequency I mentioned: 1, 2, 3
• Yes DRM Helper functions like drm_edp_backlight_init being used in the i915 driver like here, seem to support this. I am looking into it as well, but as of now I have limited understanding of modifying drivers. Any help would be highly appreciated.
• All 3 registers are 0x0 by default. There are no error messages on intel_reg write, the write goes through successfully. When I do an intel_reg read on the registers again, I can see the updated value. However, it doesn't visibly change the pwm frequency or the brightness. On the other hand, the 0xC6204 register which historically is the RAWCLK_FREQ shows the expected value of 0x10255000 (38.4MHz reference frequency) on intel_reg read.

Which is why I think the 0x0 values on those 3 registers are correct but the registers themselves are not the right ones for brightness/pwm control, because the pwm and brightness is very likely being communicated over the eDP DPCD AUX channel and not via these registers. I tried this dd command to check the DPCD AUX channel, but I don't know how to decode it to find the PWM frequency (if it is present here).

Please let me know how I could proceed. 

Thanks Again!

[ArchieD_Intel]

Hi Xyon,

Thank you for the update. To gain a comprehensive understanding of your system, please use the System Support Utility (SSU). This tool will generate a text file compiling all your system information. You can follow the instructions at this link and send the text file here. Help Guide for the Intel® System Support Utility.

If you have any questions, please let us know. Thank you.

Best regards,

Archie D.

Intel Customer Support Technician

[Xyon]

Thanks for the follow up Archie,

Please find attached the files generated, one from Linux and another from Windows.

[ArchieD_Intel]

Hi Xyon,

Thank you for providing the requested information. I will now further investigate this and will get back to you once a resolution is available. Thank you for your patience and understanding.

Best regards,

Archie D.

Intel Customer Support Technician

[ArchieD_Intel]

Hi Xyon,

Adjusting the embedded DisplayPort (eDP) backlight Pulse Width Modulation (PWM) on an Intel Core Ultra processor is a complex process that typically necessitates system-level modifications and may not be directly accessible via user interfaces. The eDP BKLTCTL signal can be used for backlight control, but its implementation and accessibility can differ based on the device.

Kindly contact your OEM as it involves the entire system. 

I will close this inquiry now. If you need further assistance, please submit a new question as this thread will no longer be monitored.

Best regards,

Archie D.

Intel Customer Support Technician