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Honored Contributor I
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2 Nios II with autonomous peripherals !

Hi All, 

 

I am been using a NIOS II core in my application for performing some activites. Now i wish to add another NIOS II to do a independent activity in the same application, which i am currently doing using VHDL block.  

 

I went through the document on multiple processors from altera but it concentrates on making a shared memory application. in case of separate memories for the processors can anyone let me know how to proceed with the qsys and the software ? 

 

Regd Software i currently first JTAG the Quartus Code. Then Run the C code from Eclipse as Hardware and download it using JTAG cable. 

 

Thanks in advance. This is an urgent requirement please help.
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Honored Contributor I
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It is even easier if you don't need to share the memory between the processors. you can just instantiate the two CPUs in your QSys project and connect each one to its memory. 

Then in Eclipse you need to create two software projects, each one with its own BSP. When you create the BSP you will be able to select the CPU you want to build the project for. 

When running the software, you can also choose which CPU to use, by selecting the correct instance number. I think it is in the "target" tab.
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Honored Contributor I
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Hey Daixiwen, thanks for ur info... I got the two NIOS II processors to work in parallel !  

 

kindly let know for flash programming i have to just add the new elf along with the sof and elf which i add with single processor ?
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Honored Contributor I
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IIRC the standard flash boot code always reads its data from immediately after the main fpga image. 

So you'd need special flash boot code for the second system. 

However, if one of the processors can access the code/data space of the other, then you can arrange for its flash boot code to load all the memory areas for both processors, and have it release the other cpu from soft-reset once this is complete. 

You'll need to use __attribute__(section("xxx")) to get the code/data into the right memory areas, make sure the linker script assigns them correctly, and that the boot loader loads them directly to the required places.
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Honored Contributor I
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Can you kindly clarify the flash part. I am not a pro in this  

 

Let me tell you what am doing now. With one NIOS II i used to, add the sof and elf (with offset equal to the size of SOF file) files using FLASH PROGRAMMER in NIOS ECLIPSE IDE and start it. This writes the files into the flash. And the code boots directly from EPSC device every power UP. 

 

Now with two NIOS codes to be written in flash..... i am facing the issue. I can understand from the previous reply that i have tell the EPCS device what to boot and when ! But can you elaborate how to do this. I am confused. 

 

Note that by JTAG'ing the SOF and 2 ELFs the code is working fine for me.
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Honored Contributor I
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I can't give you any explicit details because I don't use the IDE or boot from flash.

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Honored Contributor I
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@dsl.... ya its ok i am getting only a vague idea and not clear with things.. thats why asked... anyways anyone else outhere ! please help asap... it would be great if am able to get this done as my project is held because of this.... i will try to understand the same parallely and get back in case i cracked it.

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Honored Contributor I
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In fact the software never boots up directly from the EPCS, it would be too slow. When you select the Nios II CPU reset vector to the EPCS controller, the CPU will in fact execute a bootloader that is present in the EPCS controller itself (i.e. in a ROM block in the FPGA). This bootloader will then access the EPCS flash, copy the data to RAM, and ask the CPU to jump to the start address in RAM. The CPU never execute the application directly from the EPCS. The process (and alternative methods) are described here: http://www.altera.com/support/examples/nios2/exm-alt-boot-methods.html (there is a link to a PDF document on the page). 

What the Nios programmer do in fact is check how long the FPGA image is in the EPCS flash, and adds just after it data chunks taken from the .elf file that the bootloader can read and recopy to RAM. 

Now if you want to have the software from both CPUs in the flash you need to do at least a part of this job yourself. There are several solutions:[list][*]if both CPUs are executing the application from external RAM, you need to copy both applications from the flash to the external RAM. Again there are two methods:[list][*]keep CPU2 in reset, have CPU1 load both applications to RAM from the EPCS, and then start CPU2[*]have both CPUs read from the EPCS, but CPU2 must wait for CPU1 to be finished, and it must know where to look in the EPCS for its application[/list][*]if CPU1 uses an external RAM and CPU2 internal RAM (on-chip memory), then you can have CPU1 boot as usual with the default bootloader, and convert the CPU2's application to the .hex format. This .hex file can then be used in the Quartus project to initialize the on-chip memory, and the CPU2 can directly start on it once the FPGA is configured[/list]
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Honored Contributor I
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--- Quote Start ---  

 

Now if you want to have the software from both CPUs in the flash you need to do at least a part of this job yourself. There are several solutions:[list][*]if both CPUs are executing the application from external RAM, you need to copy both applications from the flash to the external RAM. Again there are two methods:[list][*]keep CPU2 in reset, have CPU1 load both applications to RAM from the EPCS, and then start CPU2[*]have both CPUs read from the EPCS, but CPU2 must wait for CPU1 to be finished, and it must know where to look in the EPCS for its application[/list][*]if CPU1 uses an external RAM and CPU2 internal RAM (on-chip memory), then you can have CPU1 boot as usual with the default bootloader, and convert the CPU2's application to the .hex format. This .hex file can then be used in the Quartus project to initialize the on-chip memory, and the CPU2 can directly start on it once the FPGA is configured[/list] 

--- Quote End ---  

 

 

Dear Daixiwen, thanks for this information....  

 

  • I preferred the second option mentioned by you. Ok I am doing the following now, I have compiled Quartus II with Two NIOS Processors - One in SRAM and other in On-Chip... As u mentioned i converted the second ELF file to memory initialization file. I followed the method mentioned in this page (http://www.labbookpages.co.uk/fpgas/alterahowtos/simpleniosii.html) to copy the qip file of the memory initialization to Quartus. 

  • I used Flash programmer to add SOF and ELF file of the Processor (which was supposed to be on SRAM). I added ELF Offset = Size of SOF. (703664 bytes - i converted it to HEX and entered 0xABCB0 in ELF Offset) The Flash programming is completed without error.  

  • It is copying the SOF correctly, as i am able to see the outputs of the SOF. The flash is not getting copied in the desired location i guess as Processor outputs are not coming. 

 

 

Kindly help me out of this. Correct me if i was wrong in any step. 

 

:confused:
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Honored Contributor I
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The flash programmer automatically determines the offset to the elf file, normally you should just have it burn both the FPGA image and the application at the same time, and the programmer will concatenate them. You shouldn't need to define an offset.

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Honored Contributor I
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@Daixiwen, ok I got the HEX (of second processor ELF) file pre-loaded in OnChip RAM to work in JTAG mode. I am still checking the flash programmer part which is still not successful. Wil check and get back.

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Honored Contributor I
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TO_BE_DONE

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Honored Contributor I
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Hey.... I got the system to work. This is wat i did.... 

 

> The NIOS II Processor's Reset vector was pointing to EPCS device and Exception Vector was also Pointing to EPCS device 

> Program memory was pointing to SRAM 

> I Changed the Exception vector to an Onchip memory and now the flash programmer is working fine. 

 

Any idea why it needs to be defined like this ?
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Honored Contributor I
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The exception vectors need to be in a RAM because they are initialized by the software just before jumping to main(). If you put them to a ROM then the initialization software can't write the correct ISR vector and the CPU would probably crash at the first raised interrupt. 

I'm glad you got it to work!
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