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Hi all,
I want to write program into the flash provided on my board.The FPGA chip on the board is Cyclone 1C6Q.When I followed the document of "Nios II Flash Programmer User Guide" and till the tep of Compilation, I found some err info(during Fittering;Synthesizing was OK): ------------------------------- Error: Can't place 124 RAM cells or portions of RAM cells in design ------------------------------- So I think this might be caused by the limited size of the on chip memory,it seems that the memory available can not provide enough enough space for the on chip ROM in the design("my_new_board"). However,I *did* follow the instructions in the document, and successfully made my target board based on the board with the designated buffer_size at 4096. But the doc does not give this "possible" result(err when fittering), http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/huh.gif So what I can do next? Thank you for your suggestions in advance! Regards, DonLink Copied
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I also had this problem when creating a target board for a 1C6 using 4096 buffer _size. I tried 1024 and it worked OK.
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if u use quartus 4.1 ,there will be no error!
I guess u use 4.2 or 5.0!- Mark as New
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Thank you!
That's right,now I 'm using QuartusII5.0+NiosII5.0. I readjusted the buffer_size to 2048,it seemed that everything was OK http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif- Mark as New
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There is another way to solve this problem.
This problem came out because of the lack of the RAM cells. The Jtag component can use the resource of RAM cells instead of LE cells. You can make it using the LE cells, so that the RAM cells can be used by other component. Double click the jtag component in SOPC build, and disable the options.- Mark as New
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Ha, thank you! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/tongue.gif
I really don't know this alternative approach before you told me!
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