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Altera_Forum
Honored Contributor I
747 Views

A problem in a custom component

Hello every body; 

I have created a pipelined custom component that have ReadDataValid signal, I want to read from this component by its base address. 

Is it neccessary to make a macro that samples the "ReadDataValid" signal, or I can read from it by the simple IoRead() instruction. 

Thanks.
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3 Replies
Altera_Forum
Honored Contributor I
26 Views

As long as the master connected to our component follows the Avalon specification, such as the Nios CPU, then you don't have to do anything special to handle the ReadDataValid signal. Just use the regular methods to access your component.

Altera_Forum
Honored Contributor I
26 Views

Thanks Mr Daixiwen for your attention;

Altera_Forum
Honored Contributor I
26 Views

What Daixiwne said is correct, instead of worrying about the master that will be connected to the slave, ensure that you follow the Avalon-MM specification when designing the slave. The idea behind the spec is that you don't have to worry about the connectivity between the master and slave, if you design towards the spec then the tools or IP on the other side will take care of the rest.

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