A question on Addressing of peripherals in Qsys

[Altera_Forum]

Hi, 

 background: I have generated a Qsys system. There is a 8 bit Pio in the design. After completion of the design, I assigned system address automatically.  the situation is: system is assigning an address space from x11020 to x1102f to this PIO, which makes 16 different addresses.  and the question is: Why for a single 8 bit PIO, the system is assigning 16 addresses? why? Isn't that a wastage of resources? or something there which I am missing?   Thanks in advance.   Cheers  Tahir

[Altera_Forum]

You need to read the documentation for the PIO core. First the PIO core uses 32 bit registers, independently of how many actual PIO bits you have. Then you have several 32-bit registers. The registers at offset 0 is of course to read or write the PIO bits, but then you have others related to edge detection or interrupt generation. 

When you say waste of resources, if you mean waste of logic elements in the FPGA, if you disabled all the extra features in the PIO that you don't need then the registers won't be synthesized and you won't waste logic. If you are talking about address space then yes you are wasting a bit but if you are really that tight in address space usage then you should probably design your own PIO that would just use one register. But the PIO core is using only 16 bytes out of a 4294967296 bytes address space. It's really not that much.