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12453 Discussions

A shared custom Instruction between Nios II processors

Altera_Forum
Honored Contributor II
1,131 Views

Hello everybody, 

 

I want to Implement a shared Custom Instruction Hardware(a shared Accelerator) which connects directly to the Nios II arithmetic logic unit (ALU).  

In fact, I want to know how to add this shared custom instruction between two NiosII processors.  

Thanks in advance.
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4 Replies
Altera_Forum
Honored Contributor II
83 Views

You need to add it separately to each cpu - giving you two copies of the custom instruction logic. 

You can then access external (to the custom instruction) logic.
Altera_Forum
Honored Contributor II
83 Views

So as dsl mentioned, you really need to have one instance per CPU or you need to do more work. 

 

Qsys, unfortunately, will allow you connect both NIOS Custom Instruction Master ports to your single Custom Instruction Slave port, but when it generates the system you will find that only one of them actually got connected. 

 

This type of sharing is probably better suited to an Avalon-MM Slave style IP where Qsys will correctly add the automatic arbitration logic for you. 

 

Or if you wish, you could probably add the Custom Instruction arbitration logic yourself: either create a new IP block with (2) CI Slave and (1) CI Master connected to your current IP; or alternatively you could simply add a second CI Slave port to your existing IP block and perform the arbitration internally.
Altera_Forum
Honored Contributor II
83 Views

Hi, 

Thank you for your reply. But, could you please explain more what you mean by " alternatively you could simply add a second CI Slave port to your existing IP block and perform the arbitration internally." 

You mean that i can made simply an accelerator as custom IP and i make it a dual port peripheral. 

Or you mean for a custom instruction, i can associate a vhdl block with two slave ports and then the vhdl block of this custom instruction could be accessed by two CPU?
Altera_Forum
Honored Contributor II
83 Views

You need to have two custom instruction interfaces, one for each cpu. 

Internally you could have arbitration for some shared logic. 

If you don't understand why you'll never succeed.
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