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Altera_Forum
Honored Contributor I
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A10 es hps qspi boot ddr calibration problem

Hello, 

 

I have a problem booting the A10es SoC board from QSPI. During the boot process, I can see through UART, that CPU is hanging during DRAM calibration process of the bootloader.  

 

First of all: currently, my project is not aimed to use FPGA part of the SoC at all, i'm just trying to start with HPS part currently. 

 

If i understand correctly, the FPGA part should be configured anyway, even if i just want to connect HPS with DDR memory. Also, i'm assuming, that preloader, as a part of EDS, is made by competent engineers, and should work "out of the box". 

This means, that the only part which can be incorrect, is how i'm generating "HPS to DRAM through EMIF" design in Quartus, and especially in QSYS. Is there some design, or example, which demonstrates how to simply connect HPS to DRAM? 

 

I will kindly ask You for Your help: 

1) If You can, share a project with proper HPS to DDR connection. 

2) Can A10 es SoC properly boot from QSPI and calibrate DDR4 RAM? Which version of Quartus and EDS should i have to do that? 

 

Thanks in advance!
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