Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12409 Discussions

ADC modelling in AMS SystemcTLM

Honored Contributor II

The task is to model only the ADC peripheral of the ARM cortex processor (ATSAM3S4A). I have to use the AMS library in order to model the Analog part using timed dataflow. After that, I should connect it to a master module using a TLM interface (blocking or non blocking). This master module should connect to the slave ADC slave peripheral using TLM initiator-target communication. It should perform the following functions through the programmer view: ADC_Configuration, ADC_GetStatus, ADC_GetData. I only need to use the channels 3,5 and 7. Then I should connect Sine, Cosine, and Saw tooth waves respectively using the AMS TDF. The interrupt and timer counter logic is not needed for this task. I should use a header file with the set of registers starting at address 0x40038000 in order to let the SW functions to access the ADC. When these ADC functions execute in the master module, a transaction should be triggered to the ADC slave using the TLM2 protocol. Finally I need to trace the input signals and also the digital conversion of each one in a VCD file. This ADC is 12 bits and it is required to handle single ended inputs.  


So the question would be, how do I start? I'm a total newbie, I would appreciate any help or clue in order to tackle this problem. Image
0 Kudos
1 Reply
Honored Contributor II

I think you are on the wrong forum. This forum is about Altera components.