Hi,My question is regarding the HPS core in Cyclone V SoC. I have successfully built and run sample code that came with ARM DS 5 using USB Blaster II interface. The code by default runs on 64K scratch RAM but my target application would not fit in that space. I would need a script to initialize DDR RAM accessible via the SDRAM controller so that I can load and execute my code from there. Is there any sample script available to do appropriate initialization for this scenario? I know its not too hard to write one but it'd save some time (which is of essence in my project) if there something already available. Thanks!
Dear ashahid,- What "sample code" you run? - As I know from responses of Altera SR that sw engineer should be manually changes all script files: .ld, .ds, .makefile under ARM DS-5 EDS SoC. Examine your .ld (linker script) and .ds (debug script) files for details. OCRAM (64K) started from 0xffff_0000 -> move to HPS DDR3 RAM started from 0x0100_0000 (1 GB). I hope it will help. Regards, ZS.V.
Thanks for your reply voroshazi, I ran *Altera-SoCFPGA-HelloWorld-Baremetal-ARMCC* that came with DS 5 installation.I think I'd probably need to integrate the Preloader code in my baremetal application (which is approx 300MB ). Similar to the way its being used in *Altera-SoCFPGA-HardwareLib-GNU*. I think I'd need the Preloader to initialize the SDRAM part and then direct it to load my image on SDRAM. If there's a better approach, I'd love to hear about it.
My understanding is the preloader should copy your baremetal application into SDRAM and then jump over and start running your application out of SDRAM. Otherwise your combined preloader & baremetal application would have to fit into 60K.
This is interesting, I'm working with a Cyclone V board but there isn't a board specific example how to use hardware.The HPS has 2 ddr3 SRDAM chips and the FPGA also has 2 DDR3 SdRAM chips. How do we write to the controller in binary mode using a constant pointer? I'd like to load up SDRAM but be able to write the hardware based on bytes in SDRAM. There was no hardware library for this board, so I have to implement constant pointers to registers. Is there SDRAM0 and SDRAM1 variables or what are the variables used in ARM DS-5 for all hardware?
Dear ixpress,I think this is not in the "bootloading" topic. On Cyc V SoC DB, both the HPS-side memory controller , and FPGA-side memory controller has 1-1 GBs of DDR3 memory capacity. -If HPS side SDRAM is used I suggest to examine altera applications (after a properly installed Quartus + DS5 AE): <installed_altera_dir>\embedded\examples\software -If FPGA-side SRAM is used, I suggest to examine built-in template applications in NiosII_EDS. See memory_test template example. Formerly, I have successfully tried this above memory test template on baremetal level (ARM) with replacing of some SOCAL/HWLIB functions. See: <installed_altera_dir>\embedded\ip\altera\hps\altera_hps\doc\ (two different index.htmls) Best regards, Zsolt
It is odd but none of Altera software is working on any of my computers so I have to find a way to read and write all memory locations of the board in binary.This might not be too difficult. Perhaps the FPGA can be reconfigured in real time for different applications by the HPS. If a virtual USB terminal is possible, maybe it would be possible to read/write all memory locations.