AS/JTAG mode by using file type pof , how to connect the MSEL[2:0]?

[SFeng5]

Hi everybody

I'm a FPGA hardware beginner

I have a question that I have a EEPROM and fpga

when the power start the EEPROM will write the data to fpga

so I need to using AS mode or JTAG mod or PS mode

I have three data type: sof , pof , jic

component used:

EEPROM :EPCS16

FPGA:EP3C16F256

MSEL0:gnd

MSEL1:Vref

MSEL2:gnd

I using usbBlaster and JTAG mode can flash the sof to FPGA but that data is in SRAM when I close off the power the data will disappear.

​

I try to using jic but when I flashing it the error is occurred as shown:

Can't recognize silicon ID for device 1

I try to using pof but I can't add the file on the quartus programming page:

cannot add flash memory programmer object file at the top level​

​

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大家好

想詢問一下FPGA AS mode PS mode JTAG mode的使用方法

好像有個選擇的多工器MSEL[2:0]我現在的接法是

msel0:low

msel1:high

msel2:low​

用了三種檔案格式

SOF

POF

JIC

只有SOF成功燒錄，但RESET就消失了

JIC檔案不知道為什麼燒錄到一半都會出現​

Can't recognize silicon ID for device 1

POF則是在programming頁面add file時出現(不管MODE是JTAG或Active Serial Programming

cannot add flash memory programmer object file at the top level​

[AnandRaj_S_Intel]

HI,

1. Have used correct programming headers ? For .jic file, you have to use JTAG header & .pof use AS header. You also may get this error if you have a noisy TCK signal or if the JTAG or AS header are not powered with the correct voltage.
2. Have you select correct mode while generating pof? it should be Fast Active Serial Standard ASX1.

Regards

Anand

[Abe]

These pins are internally connected to 5-KΩ resistor to GND. Do not leave these pins floating. When these pins are unused connect them to GND. Depending on the configuration scheme used, these pins should be tied to VCCA or GND. Refer to Chapter 9 of Cyclone III Device Family Handbook: Configuration, Design Security, and Remote System Upgrades in Cyclone III Devices. If only JTAG configuration is used, then connect these pins to GND.

You can also try the following:

Disconnect the pin 6 of the JTAG connector and short nCE of the FPGA to GND without the 10K resistor.