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AXI Transaction Timing in HPS busses

Altera_Forum
Honored Contributor II
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I'm hoping that someone could help me out here in figuring out how atomic accesses are processed in Linux when accessing the lightweight bus. As an example: 

 

The lightweight bus is running at 60 MHz, and the HPS at 800 MHz, with an L3 bus speed of 185 MHz. Supposing I do a single register read of a memory-mapped register, doesn't this mean that the thread will be blocked for at least (n * 60MHz) clock cycles? And does this mean that the kernel is also blocked, or is the Linux kernel able to run other threads doing other L3 device memory accesses until the read is done? I know that on an RTOS these reads would be atomic, and definitely would block the kernel until complete. 

 

If someone knows where in the ARM kernel code the memory accesses are defined, I can probably work it out from there as well. 

 

Thanks!
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